The important gate driver characteristics are as follows: Pull-down resistance as low as 0.5Ω With dV/dt slew rates of 20-30V/ns or more, the risk of Miller turn-on and shoot-through becomes a concern for the higher voltage devices. The gate drive pull-down resistance must be minimized for maximum dV/dt immunity. An accurate gate drive supply voltage: There is only a one-Volt headroom between the recommended gate overdrive voltage (5V) and the absolute maximum rating (6V). This accuracy requirement is more difficult to achieve for a bootstrapped supply. Adjustable pull up resistance for EMI and voltage overshoot control: For half-bridge applications for MOSFETs, a resistor with an anti parallel diode is typically used for this purpose. For eGaN, the need for minimizing pull-down resistance means that this resistor and anti parallel diode connection is not recommended. The simplest general solution is to split the gate pull-up and pull-down connections and allow the insertion of a discrete resistor as needed. Low gate drive loop impedance: At these high switching speeds, the impact of the gate drive interconnection impedance also becomes important – requiring the gate drive to be placed as close as possible to the eGaN power device.