ECP3 Family DataSheet V1.6 by Lattice Semiconductor Corporation

LatticeECP3 Family Data Sheet

Preliminary DS1021 Version 01.6, March 2010

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

Lattice“ emiconguctor Corporation e multiply 5 MAC Sharing Half 36x36, Mo 18x18 orlour 9x9 multipliers Advanced 18x36 MAC and 18x18 Multiply- Multiplyercumulaie (MMAC) operations emory Resources .85Mbits sysMEMWI Embedded Block M (EBFl) K to 303K bits distributed RAM ysCLOCK Analog PLLs and DLLs I Two DLLs and up to ten PLLs per device Pre-Engineered Source Synchronous llO I DDR registers in 1/0 cells Table 1-1. LatticeECF'I!m Family Selection Guide levelling functionality ogic onous standards support /DAC, 7:1 LVDS, XGMII Speed ADC/DAG dewces cated DDR/DDRZ/DDRS memory with DQS ppon I Optional Inter-Symbol Interference (ISI) correction on outputs Programmable sysllC)”I Butfer Supports Wide Range ot Interfaces I Onrchrpiermination I Optional equalization lilter on inputs I LVlTL and LVCMOS 33/25/18/15/12 I SSTL 33/2511 8/15 I, II I HSTL15 | and HSTL18 I, II I PCI and Differential HSTL, SSTL I LVDS, BusrLVDS, LVPECL, RSDS, Flexible Device Conﬁguration I Dedicated bank for configuratio I SPI boot llash interface I Dualrboot images supported I Slave SPI I TransFFt'"I IIO for simple I Soft Error Detect e System Level Supp I IEEE 1149.1 I Reveal Logic I ORCAs I Onrchip I 1. Device ECP3-17 ECPG— LUTs (K) 17 sysMEM Blocks (18Kbiis) 38 Embedded Memory (Kbits) 700 Distributed RAM Bits (Kbits) 36 18x18 Multipliers 24 SERDES (Quad) PLLs/DLLs Packages and SERDES Channel 256 ftBGA (17x17 mm)

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November 2009 Preliminary Data Sheet DS1021

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

Features

Higher Logic Density for Increased System

Integration

• 17K to 149K LUTs

• 133 to 586 I/Os

Embedded SERDES

• 150 Mbps to 3.2 Gbps for Generic 8b10b, 10-bit

SERDES, and 8-bit SERDES modes

• Data Rates 230 Mbps to 3.2 Gbps per channel

for all other protocols

• Up to 16 channels per device: PCI Express,

SONET/SDH, Ethernet (1GbE, SGMII, XAUI),

CPRI, SMPTE 3G and Serial RapidIO

sysDSP™

• Fully cascadable slice architecture

• 12 to 160 slices for high performance multiply

and accumulate

• Powerful 54-bit ALU operations

• Time Division Multiplexing MAC Sharing

• Rounding and truncation

• Each slice supports

– Half 36x36, two 18x18 or four 9x9 multipliers

– Advanced 18x36 MAC and 18x18 Multiply-

Multiply-Accumulate (MMAC) operations

Flexible Memory Resources

• Up to 6.85Mbits sysMEM™ Embedded Block

RAM (EBR)

• 36K to 303K bits distributed RAM

sysCLOCK Analog PLLs and DLLs

• Two DLLs and up to ten PLLs per device

Pre-Engineered Source Synchronous I/O

• DDR registers in I/O cells

• Dedicated read/write levelling functionality

• Dedicated gearing logic

• Source synchronous standards support

– ADC/DAC, 7:1 LVDS, XGMII

– High Speed ADC/DAC devices

• Dedicated DDR/DDR2/DDR3 memory with DQS

support

• Optional Inter-Symbol Interference (ISI) 

correction on outputs

Programmable sysI/O™ Buffer Supports

Wide Range of Interfaces

• On-chip termination

• Optional equalization filter on inputs

• LVTTL and LVCMOS 33/25/18/15/12

• SSTL 33/25/18/15 I, II

• HSTL15 I and HSTL18 I, II

• PCI and Differential HSTL, SSTL

• LVDS, Bus-LVDS, LVPECL, RSDS, MLVDS

Flexible Device Configuration

• Dedicated bank for configuration I/Os

• SPI boot flash interface

• Dual-boot images supported

• Slave SPI

• TransFR™ I/O for simple field updates

• Soft Error Detect embedded macro

System Level Support

• IEEE 1149.1 and IEEE 1532 compliant

• Reveal Logic Analyzer

• ORCAstra FPGA configuration utility

• On-chip oscillator for initialization & general use

• 1.2V core power supply

Table 1-1. LatticeECP3™ Family Selection Guide

Device ECP3-17 ECP3-35 ECP3-70 ECP3-95 ECP3-150

LUTs (K) 17336792149

sysMEM Blocks (18Kbits) 38 72 240 240 372

Embedded Memory (Kbits) 700 1327 4420 4420 6850

Distributed RAM Bits (Kbits) 36 68 145 188 303

18X18 Multipliers 24 64 128 128 320

SERDES (Quad) 11334

PLLs/DLLs 2 / 2 4 / 2 10 / 2 10 / 2 10 / 2

Packages and SERDES Channels/ I/O Combinations

256 ftBGA (17x17 mm) 4 / 133 4 / 133

484 fpBGA (23x23 mm) 4 / 222 4 / 295 4 / 295 4 / 295

672 fpBGA (27x27 mm) 4 / 310 8 / 380 8 / 380 8 / 380

1156 fpBGA (35x35 mm) 12 / 490 12 / 490 16 / 586

LatticeECP3 Family Data Sheet

Introduction

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

ed, lowicost applications. ogic elements and supports up to multipliers and a wide range of parallel low cost in mind. The LatticeECP3 deVices building blocks such as LUTrbased logic, distribr elay Locked Loops (DLLs), prerengineered source advanced configuration support, including encryption and emented in the LatticeECP3 device family supports a broad II and 7:1 LVDS. gh speed SERDES with dedicated PCS functions. High jitter tolerr DES plus PCS blocks to be configured to support an array of po SMPTE, Ethernet (XAUI, GbE, and SGMII) and CPRI. Transmit Prer make the SERDES suitable tor transmission and reception provide flexible, reliable and secure conﬁguration options, such a and TransFFt field upgrade features. tool suite from Lattice allows large complex designs to be eﬂicientl family. Synthesis library support for LatticeECP3 is available for tool uses the synthesis tool output along with the constraints lrom it esign in the LatticeECPS deVice. The ispLEVEFt tool extracts th it into the design for timing verification. e prowdes many prerengineered IP (Intellectual Property) ispLeve y. By using these configurable soft core lPs as standardized blocks, idue aspects ol their design, increasing their productivity.

1-2

Introduction

Lattice Semiconductor LatticeECP3 Family Data Sheet

Introduction

The LatticeECP3™ (EConomy Plus Third generation) family of FPGA devices is optimized to deliver high perfor-

mance features such as an enhanced DSP architecture, high speed SERDES and high speed source synchronous

interfaces in an economical FPGA fabric. This combination is achieved through advances in device architecture

and the use of 65nm technology making the devices suitable for high-volume, high-speed, low-cost applications.

The LatticeECP3 device family expands look-up-table (LUT) capacity to 149K logic elements and supports up to

486 user I/Os. The LatticeECP3 device family also offers up to 320 18x18 multipliers and a wide range of parallel

I/O standards.

The LatticeECP3 FPGA fabric is optimized with high performance and low cost in mind. The LatticeECP3 devices

utilize reconfigurable SRAM logic technology and provide popular building blocks such as LUT-based logic, distrib-

uted and embedded memory, Phase Locked Loops (PLLs), Delay Locked Loops (DLLs), pre-engineered source

synchronous I/O support, enhanced sysDSP slices and advanced configuration support, including encryption and

dual-boot capabilities.

The pre-engineered source synchronous logic implemented in the LatticeECP3 device family supports a broad

range of interface standards, including DDR3, XGMII and 7:1 LVDS.

The LatticeECP3 device family also features high speed SERDES with dedicated PCS functions. High jitter toler-

ance and low transmit jitter allow the SERDES plus PCS blocks to be configured to support an array of popular

data protocols including PCI Express, SMPTE, Ethernet (XAUI, GbE, and SGMII) and CPRI. Transmit Pre-empha-

sis and Receive Equalization settings make the SERDES suitable for transmission and reception over various

forms of media.

The LatticeECP3 devices also provide flexible, reliable and secure configuration options, such as dual-boot capa-

bility, bit-stream encryption, and TransFR field upgrade features.

The ispLEVER® design tool suite from Lattice allows large complex designs to be efficiently implemented using the

LatticeECP3 FPGA family. Synthesis library support for LatticeECP3 is available for popular logic synthesis tools.

The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place

and route the design in the LatticeECP3 device. The ispLEVER tool extracts the timing from the routing and back-

annotates it into the design for timing verification.

Lattice provides many pre-engineered IP (Intellectual Property) ispLeverCORE™ modules for the LatticeECP3

family. By using these configurable soft core IPs as standardized blocks, designers are free to concentrate on the

unique aspects of their design, increasing their productivity.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

Latticei emiconductor Corporation ogrammable l/O Cells (PIC). lnterr ed Block RAM (EBR) and rows of sysr tion, the LatticeECPS family contains Unit (PFU) and Programmable Functional Unit gic, arithmetic, RAM and ROM functions. The PFF M functions. Both PFU and PFF blocks are optimized for ckly and efﬁciently. Logic Blocks are arranged in a two r row. of sysMEM EBR blocks. sysMEM EBRs are large, dedicated ck can be conﬁgured in a variety of depths and moths as RAM or up to two rows of DSP slices. Each DSP slice has multipliers and blocks for complex signal processing capabilities. 16 embedded 3.2Gbps SERDES (Serializer / Deserializer) cha dent 8b/10b encoding / decoding, polarity adjust and elastic buffe along with its Physical Coding Sub-layer (PCS) block, creates uads can be controlled by memory cells set during device configu during device operation. The registers in every quad can be pro face (SCI). These quads (up to four) are located at the bottom of the ompasses two PlOs (PIO pairs) with their respective sysl/O but evices are arranged in seven banks, alIoWing the implementation of a separate l/O bank is prowded for the programming intertaces. 5 s ol the device can be configured as LVDS transmit/receive pairs. T upport to aid in the implementation of high speed source sync S, along with memory interfaces including DDR3. her blocks provided include PLLs, DLLs and configuration funct ay Locked Loops (DLLs) and up to ten Phase Locked Loops ber provides two DLLs per device. The PLL and DLL blocks are The configuration block that supports features such as co and dualrboot support is located toward the center 0 ports a sysCONFIGWI port located in the corner bet device conﬁguration. In addition, every deVice in the family has a detect capability. The Lat‘liceECPS devices

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March 2010 Preliminary Data Sheet DS1021

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

Architecture Overview

Each LatticeECP3 device contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Inter-

spersed between the rows of logic blocks are rows of sysMEM™ Embedded Block RAM (EBR) and rows of sys-

DSP™ Digital Signal Processing slices, as shown in Figure 2-1. In addition, the LatticeECP3 family contains

SERDES Quads on the bottom of the device.

There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Functional Unit

without RAM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM and ROM functions. The PFF

block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks are optimized for

flexibility, allowing complex designs to be implemented quickly and efficiently. Logic Blocks are arranged in a two-

dimensional array. Only one type of block is used per row.

The LatticeECP3 devices contain one or more rows of sysMEM EBR blocks. sysMEM EBRs are large, dedicated

18Kbit fast memory blocks. Each sysMEM block can be configured in a variety of depths and widths as RAM or

ROM. In addition, LatticeECP3 devices contain up to two rows of DSP slices. Each DSP slice has multipliers and

adder/accumulators, which are the building blocks for complex signal processing capabilities.

The LatticeECP3 devices feature up to 16 embedded 3.2Gbps SERDES (Serializer / Deserializer) channels. Each

SERDES channel contains independent 8b/10b encoding / decoding, polarity adjust and elastic buffer logic. Each

group of four SERDES channels, along with its Physical Coding Sub-layer (PCS) block, creates a quad. The func-

tionality of the SERDES/PCS quads can be controlled by memory cells set during device configuration or by regis-

ters that are addressable during device operation. The registers in every quad can be programmed via the

SERDES Client Interface (SCI). These quads (up to four) are located at the bottom of the devices.

Each PIC block encompasses two PIOs (PIO pairs) with their respective sysI/O buffers. The sysI/O buffers of the

LatticeECP3 devices are arranged in seven banks, allowing the implementation of a wide variety of I/O standards.

In addition, a separate I/O bank is provided for the programming interfaces. 50% of the PIO pairs on the left and

right edges of the device can be configured as LVDS transmit/receive pairs. The PIC logic also includes pre-engi-

neered support to aid in the implementation of high speed source synchronous standards such as XGMII, 7:1

LVDS, along with memory interfaces including DDR3.

Other blocks provided include PLLs, DLLs and configuration functions. The LatticeECP3 architecture provides two

Delay Locked Loops (DLLs) and up to ten Phase Locked Loops (PLLs). In addition, each LatticeECP3 family mem-

ber provides two DLLs per device. The PLL and DLL blocks are located at the end of the EBR/DSP rows.

The configuration block that supports features such as configuration bit-stream decryption, transparent updates

and dual-boot support is located toward the center of this EBR row. Every device in the LatticeECP3 family sup-

ports a sysCONFIG™ port located in the corner between banks one and two, which allows for serial or parallel

device configuration.

In addition, every device in the family has a JTAG port. This family also provides an on-chip oscillator and soft error

detect capability. The LatticeECP3 devices use 1.2V as their core voltage.

LatticeECP3 Family Data Sheet

Architecture

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

es Onthlp cscmamr Prerenglneered Source Synchronous Suppon. DDRSV BUOMst Genenc , Up to rebps Flexible syslc wcmos HST ssTL up to 4 sannzsrpc SERnEsIPcS mm en a on 1 en a T5 :ysz Banks Nole There rs no Bank a or Bank 5 m LamceECPS devrces PFU Blocks The core of the LaniceECPS device consrsts of PFU The PFUs can be programmed to perform Logrc blocks can be programmed to perform Logrc, Ari der of ms data sheet will use the term PFU Each PFU block consists of four imer two LUTs. AM the rnterconneotions to associated with each PFU block

2-2

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

Figure 2-1. Simplified Block Diagram, LatticeECP3-35 Device (Top Level)

PFU Blocks

The core of the LatticeECP3 device consists of PFU blocks, which are provided in two forms, the PFU and PFF.

The PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF

blocks can be programmed to perform Logic, Arithmetic and ROM functions. Except where necessary, the remain-

der of this data sheet will use the term PFU to refer to both PFU and PFF blocks.

Each PFU block consists of four interconnected slices numbered 0-3 as shown in Figure 2-2. Each slice contains

two LUTs. All the interconnections to and from PFU blocks are from routing. There are 50 inputs and 23 outputs

associated with each PFU block.

SERDES/PCS

CH 3

SERDES/PCS

CH 2

SERDES/PCS

CH 1

SERDES/PCS

CH 0

sysIO

Bank

sysIO

Bank

sysIO

Bank 0

sysIO

Bank 1

sysIO Bank 3 sysIO Bank 6

Configuration Logic:

Dual-boot, Encryption

and Transparent Updates

On-chip Oscillator

Pre-engineered Source

Synchronous Support:

DDR3 - 800Mbps

Generic - Up to 1Gbps

Flexible Routing:

Optimized for speed

and routability

Flexible sysIO:

LVCMOS, HSTL,

SSTL, LVDS

Up to 486 I/Os

Programmable

Function Units:

Up to 149K LUTs

sysCLOCK

PLLs & DLLs:

Frequency Synthesis

and Clock Alignment

Enhanced DSP

Slices: Multiply,

Accumulate and ALU

JTAG

sysMEM Block

RAM: 18Kbit

3.2Gbps SERDES

Note: There is no Bank 4 or Bank 5 in LatticeECP3 devices.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

To Routing Slice 3 UT4s leeding two registers, whereas Slice 3 contains two LUT n be configured as distributed memory, a capability not available ol the slices in both PFF and PFU blocks along with the oper FU contains logic that allows the LUTs to be combined to perform T8. There is control logic to perform set/reset functions (program elect, chiprselect and wider RAM/ROM lunctions. es and Modes Available per Slice PFU BLock Resources Modes Resourc Slice 0 2 LUTAs and 2 Registers Logic, Ripple, RAM, ROM 2 LUTAs a Slice 1 2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 LU Slice 2 2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 Slice 3 2 LUTAs Logic, ROM Figure 273 shows an overview of the internal logic of the sli tive/negative and edge triggered or level sensitive cloc Slices O, 1 and 2 have 14 input signals: 13 signals fr slice or PFU). There are seven outputs: six to ro input signals from routing and four signals to rou

2-3

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

Figure 2-2. PFU Diagram

Slice

Slice 0 through Slice 2 contain two LUT4s feeding two registers, whereas Slice 3 contains two LUT4s only. For

PFUs, Slice 0 through Slice 2 can be configured as distributed memory, a capability not available in the PFF.

Table 2-1 shows the capability of the slices in both PFF and PFU blocks along with the operation modes they

enable. In addition, each PFU contains logic that allows the LUTs to be combined to perform functions such as

LUT5, LUT6, LUT7 and LUT8. There is control logic to perform set/reset functions (programmable as synchronous/

asynchronous), clock select, chip-select and wider RAM/ROM functions.

Table 2-1. Resources and Modes Available per Slice

Figure 2-3 shows an overview of the internal logic of the slice. The registers in the slice can be configured for posi-

tive/negative and edge triggered or level sensitive clocks.

Slices 0, 1 and 2 have 14 input signals: 13 signals from routing and one from the carry-chain (from the adjacent

slice or PFU). There are seven outputs: six to routing and one to carry-chain (to the adjacent PFU). Slice 3 has 10

input signals from routing and four signals to routing. Table 2-2 lists the signals associated with Slice 0 to Slice 2.

Slice

PFU BLock PFF Block

Resources Modes Resources Modes

Slice 0 2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 LUT4s and 2 Registers Logic, Ripple, ROM

Slice 1 2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 LUT4s and 2 Registers Logic, Ripple, ROM

Slice 2 2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 LUT4s and 2 Registers Logic, Ripple, ROM

Slice 3 2 LUT4s Logic, ROM 2 LUT4s Logic, ROM

Slice 0

LUT4 &

CARRY

LUT4 &

CARRY

D D

Slice 1

LUT4 &

CARRY

LUT4 &

CARRY

Slice 2

LUT4 &

CARRY

LUT4 &

CARRY

From

Routing

Slice 3

LUT4 LUT4

D D D D

FF FF FF FF FF FF

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

Not In SIICE 3 OFXI F1 01 To nonung OFXO F0 LUT4& CARRV' W5 00 CI FCI From Dlﬂarenl SIIce/PFU For SIIces o and I, memory control SIgnaIs are generated hom Slice 2 as I‘olIows ch .s cm WHE .s Imm LSR DI[3.2]'OYSIICE1 and DI[I o] my sm 0 data Irom Shae 2 WAD [A D] .s a 4-bit addvess tram shoe 2 LUT Input Slice Signal Descriptions Function Type Signal Names Input Data sIgnaI A0. B0. CO. D0 Inputs to LUT4 Input Data sxgnaI A1. B1. C1. D1 Inputs to LUT4 Input Multi-purpose M0 Multipurpos Input Multi-purpose M1 Multipurpos Input Control signal CE Clock E Input Contml sIgnaI LSFI I. Input Contml sxgnaI CLK S Input Intel-PFU signal FC Input Intel-slice signal FXA Input Intel-shoe signal F Output Data signals Output Data signals Output Data signals Output Data signals

2-4

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

Figure 2-3. Slice Diagram

Table 2-2. Slice Signal Descriptions

Function Type Signal Names Description

Input Data signal A0, B0, C0, D0 Inputs to LUT4

Input Data signal A1, B1, C1, D1 Inputs to LUT4

Input Multi-purpose M0 Multipurpose Input

Input Multi-purpose M1 Multipurpose Input

Input Control signal CE Clock Enable

Input Control signal LSR Local Set/Reset

Input Control signal CLK System Clock

Input Inter-PFU signal FC Fast Carry-in1

Input Inter-slice signal FXA Intermediate signal to generate LUT6 and LUT7

Input Inter-slice signal FXB Intermediate signal to generate LUT6 and LUT7

Output Data signals F0, F1 LUT4 output register bypass signals

Output Data signals Q0, Q1 Register outputs

Output Data signals OFX0 Output of a LUT5 MUX

Output Data signals OFX1 Output of a LUT6, LUT7, LUT82 MUX depending on the slice

Output Inter-PFU signal FCO Slice 2 of each PFU is the fast carry chain output1

1. See Figure 2-3 for connection details.

2. Requires two PFUs.

LUT4 &

CARRY*

SLICE

FF*

OFX0

LUT4 &

CARRY*

FF*

OFX1

F/SUM

F/SUM D

FCI From Different Slice/PFU

FCO To Different Slice/PFU

LUT5

Mux

From

Routing

For Slices 0 and 1, memory control signals are generated from Slice 2 as follows:

WCK is CLK

WRE is from LSR

DI[3:2] for Slice 1 and DI[1:0] for Slice 0 data from Slice 2

WAD [A:D] is a 4-bit address from slice 2 LUT input

* Not in Slice 3

CLK

LSR

FXB

FXA

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

ables. A LUT4 can have 16 ogramming this lookup table. ce. Larger lookrup tables such as 5. Note LUTB requires more than four tic functions. In ripple mode, the lollowmg funcr us clear (Sync) ding block ons of A and B inputs anrorrequalrto B qualrto B thanrorrequalrto B de includes an optional configuration that performs arithmetic us tion (also referred to as CCUZ mode) two additional signals, Carry G on a per slice basis to allow last arithmetic functions to be cons M Mode In this mode, a 16x4rbit distributed single port FlAM (SPFl) can b Slice 1 as a 16x1 rbit memory. Slice 2 is used to provide m dual port RAM (PDPR) memory is created by using one Sli as the readronly port. LatticeECPa deVices support distributed memory The Lattice design tools support the creation of ware will construct these using distributed shows the number of slices required to imp using RAM in LatticeECPa devices, p LatticeECPS Memory Usage Guide Table 2-3. Number of Slices H

2-5

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

Modes of Operation

Each slice has up to four potential modes of operation: Logic, Ripple, RAM and ROM.

Logic Mode

In this mode, the LUTs in each slice are configured as 4-input combinatorial lookup tables. A LUT4 can have 16

possible input combinations. Any four input logic functions can be generated by programming this lookup table.

Since there are two LUT4s per slice, a LUT5 can be constructed within one slice. Larger look-up tables such as

LUT6, LUT7 and LUT8 can be constructed by concatenating other slices. Note LUT8 requires more than four

slices.

Ripple Mode

Ripple mode supports the efficient implementation of small arithmetic functions. In ripple mode, the following func-

tions can be implemented by each slice:

• Addition 2-bit

• Subtraction 2-bit

• Add/Subtract 2-bit using dynamic control

• Up counter 2-bit

• Down counter 2-bit

• Up/Down counter with asynchronous clear

• Up/Down counter with preload (sync)

• Ripple mode multiplier building block

• Multiplier support

• Comparator functions of A and B inputs

– A greater-than-or-equal-to B

– A not-equal-to B

– A less-than-or-equal-to B

Ripple Mode includes an optional configuration that performs arithmetic using fast carry chain methods. In this con-

figuration (also referred to as CCU2 mode) two additional signals, Carry Generate and Carry Propagate, are gener-

ated on a per slice basis to allow fast arithmetic functions to be constructed by concatenating Slices.

RAM Mode

In this mode, a 16x4-bit distributed single port RAM (SPR) can be constructed using each LUT block in Slice 0 and

Slice 1 as a 16x1-bit memory. Slice 2 is used to provide memory address and control signals. A 16x2-bit pseudo

dual port RAM (PDPR) memory is created by using one Slice as the read-write port and the other companion slice

as the read-only port.

LatticeECP3 devices support distributed memory initialization.

The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the soft-

ware will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3

shows the number of slices required to implement different distributed RAM primitives. For more information about

using RAM in LatticeECP3 devices, please see TN1179, LatticeECP3 Memory Usage Guide.

Table 2-3. Number of Slices Required to Implement Distributed RAM

SPR 16X4 PDPR 16X4

Number of slices 3 3

Note: SPR = Single Port RAM, PDPR = Pseudo Dual Port RAM

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

LatticeECP3 Memory Usage Guide signals individually or as busses with y, buffers and metal interconnect (routing) t produces a compact design. The ispLEVEFt aces and routes the design. ze clock frequencies. All the devices in the LatticeECPa family LLs. ure 274. A description of the PLL functionality lollows. rated either from the pin or lrom routing) for the PLL. CLKI feeds FB is the feedback signal (generated from CLKOP, CLKOS or lrom the Feedback Divider. The Feedback Divtder is used to multiply the r edback signals enter the Voltage Controlled Oscillator (VCO) bl put path and feedback signals is used to control the lrequency and rated by the VCO to indicate that the VCO has locked onto the may lose lock after a dynamic delay adjustment and not relock until t of the VCO then enters the CLKOP divider. The CLKOP divtder allo ncies than the clock output (CLKOP), thereby increasing the frequen ts the phase and duty cycle of the CLKOS signal. The phase/duty namically adjusted. A secondary divider takes the CLKOP or CL tputs (CLKOK). The primary output from the CLKOP divider (CLKOP) along and CLKOKZ) and Phase/Duty select (CLKOS) are fed to th The PLL allows two methods for adjusting the phase This inserts up to 16 nominal 125ps delays to b be set statically or from the FPGA logic. The s allows the phase ol the rising and tailing e The number ol steps may be set statically o

2-6

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

ROM Mode

ROM mode uses the LUT logic; hence, Slices 0 through 3 can be used in ROM mode. Preloading is accomplished

through the programming interface during PFU configuration.

For more information, please refer to TN1179, LatticeECP3 Memory Usage Guide.

Routing

There are many resources provided in the LatticeECP3 devices to route signals individually or as busses with

related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing)

segments.

The LatticeECP3 family has an enhanced routing architecture that produces a compact design. The ispLEVER

design tool suite takes the output of the synthesis tool and places and routes the design.

sysCLOCK PLLs and DLLs

The sysCLOCK PLLs provide the ability to synthesize clock frequencies. All the devices in the LatticeECP3 family

support four to ten full-featured General Purpose PLLs.

General Purpose PLL

The architecture of the PLL is shown in Figure 2-4. A description of the PLL functionality follows.

CLKI is the reference frequency (generated either from the pin or from routing) for the PLL. CLKI feeds into the

Input Clock Divider block. The CLKFB is the feedback signal (generated from CLKOP, CLKOS or from a user clock

pin/logic). This signal feeds into the Feedback Divider. The Feedback Divider is used to multiply the reference fre-

quency.

Both the input path and feedback signals enter the Voltage Controlled Oscillator (VCO) block. In this block the dif-

ference between the input path and feedback signals is used to control the frequency and phase of the oscillator. A

LOCK signal is generated by the VCO to indicate that the VCO has locked onto the input clock signal. In dynamic

mode, the PLL may lose lock after a dynamic delay adjustment and not relock until the tLOCK parameter has been

satisfied.

The output of the VCO then enters the CLKOP divider. The CLKOP divider allows the VCO to operate at higher fre-

quencies than the clock output (CLKOP), thereby increasing the frequency range. The Phase/Duty Select block

adjusts the phase and duty cycle of the CLKOS signal. The phase/duty cycle setting can be pre-programmed or

dynamically adjusted. A secondary divider takes the CLKOP or CLKOS signal and uses it to derive lower frequency

outputs (CLKOK).

The primary output from the CLKOP divider (CLKOP) along with the outputs from the secondary dividers (CLKOK

and CLKOK2) and Phase/Duty select (CLKOS) are fed to the clock distribution network.

The PLL allows two methods for adjusting the phase of signal. The first is referred to as Fine Delay Adjustment.

This inserts up to 16 nominal 125ps delays to be applied to the secondary PLL output. The number of steps may

be set statically or from the FPGA logic. The second method is referred to as Coarse Phase Adjustment. This

allows the phase of the rising and falling edge of the secondary PLL output to be adjusted in 22.5 degree steps.

The number of steps may be set statically or from the FPGA logic.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

UU CLKOKZ 7&4: V V / F CLKOS Duty Cycle/ B 4b Duty Trim 4» 4> 7 r CLKOP EH 4’ Duty Trim ‘ , CLKOK Divider Lock LOCK |:>—> Detect t:>—> D i:>—> l:>—> signals in the PLL blocks. scriptians Description | Clock input from external pin or routing l PLL teedback input from CLKOP, CLKOS‘ or from a user clock (pin 0 l “1" to reset PLL counters, VCD, charge pumps and M-dividers l “1" to reset K-divider l DPA Fine Delay Adyust input 0 PLL output to clock tree (phase shifted/duty cycle CLKOP O PLL output to clock tree (no phase shift) CLKOK O PLL output to clock tree through secondary CLKOKZ O PLL output to clock tree (CLKOP divide LOCK O “1" indicates PLL LOCK to CLKI FDA [3:0] I Dynamtc tine delay adjustment on DFtPAl[3:0] l Dynamtc coarse phase shift, rising DFPAI[3:0] | Dynamic coarse phase Shl" Delay Locked Loops (DLL) In addition to PLLs, the LatticeECPS family CLKI is the input trequency (generate block to bypass the DLL, directly to th input 01 the Phase Detector (PD Chain signals. The feedback in

2-7

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

Figure 2-4. General Purpose PLL Diagram

Table 2-4 provides a description of the signals in the PLL blocks.

Table 2-4. PLL Blocks Signal Descriptions

Delay Locked Loops (DLL)

In addition to PLLs, the LatticeECP3 family of devices has two DLLs per device.

CLKI is the input frequency (generated either from the pin or routing) for the DLL. CLKI feeds into the output muxes

block to bypass the DLL, directly to the DELAY CHAIN block and (directly or through divider circuit) to the reference

input of the Phase Detector (PD) input mux. The reference signal for the PD can also be generated from the Delay

Chain signals. The feedback input to the PD is generated from the CLKFB pin or from a tapped signal from the

Delay chain.

The PD produces a binary number proportional to the phase and frequency difference between the reference and

feedback signals. Based on these inputs, the ALU determines the correct digital control codes to send to the delay

Signal I/O Description

CLKI I Clock input from external pin or routing

CLKFB I PLL feedback input from CLKOP, CLKOS, or from a user clock (pin or logic)

RST I “1” to reset PLL counters, VCO, charge pumps and M-dividers

RSTK I “1” to reset K-divider

WRDEL I DPA Fine Delay Adjust input

CLKOS O PLL output to clock tree (phase shifted/duty cycle changed)

CLKOP O PLL output to clock tree (no phase shift)

CLKOK O PLL output to clock tree through secondary clock divider

CLKOK2 O PLL output to clock tree (CLKOP divided by 3)

LOCK O “1” indicates PLL LOCK to CLKI

FDA [3:0] I Dynamic fine delay adjustment on CLKOS output

DRPAI[3:0] I Dynamic coarse phase shift, rising edge setting

DFPAI[3:0] I Dynamic coarse phase shift, falling edge setting

CLKFB

Divider

RST

CLKFB

CLKI

LOCK

CLKOP

CLKOS

RSTK

WRDEL

FDA[3:0]

CLKOK2

CLKOK

CLKI

Divider

PFD VCO/

Loop Filter

CLKOP

Divider

Phase/

Duty Cycle/

Duty Trim

CLKOK

Divider

Lock

Detect

DRPAI[3:0]

DFPAI[3:0]

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

eleck one of me ouiputs from low mis ouipui m be funher hase shifted a further 45, 22.5 or 11.25 s are available wiih opiional duty cycle ble ai CLKOS. The LOCK ompui signal is agram and Table 2-5 pmVides a descripiion of h as Iime reierence delay mode and clock injection ols ior ihese funchons. my Cyciu 97 CLKO sn-s D ,— E 4» Relay-rice Cynic 37 Em A: Iii Anmm-uc i’ Logicunlt Feemnck —>7> 37> 4:) m5 0] 3+ m ”This signal is not user accessibie This can only be used io ised me siave d

2-8

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

chain in order to better match the reference and feedback signals. This digital code from the ALU is also transmit-

ted via the Digital Control bus (DCNTL) bus to its associated Slave Delay lines (two per DLL). The ALUHOLD input

allows the user to suspend the ALU output at its current value. The UDDCNTL signal allows the user to latch the

current value on the DCNTL bus.

The DLL has two clock outputs, CLKOP and CLKOS. These outputs can individually select one of the outputs from

the tapped delay line. The CLKOS has optional fine delay shift and divider blocks to allow this output to be further

modified, if required. The fine delay shift block allows the CLKOS output to phase shifted a further 45, 22.5 or 11.25

degrees relative to its normal position. Both the CLKOS and CLKOP outputs are available with optional duty cycle

correction. Divide by two and divide by four frequencies are available at CLKOS. The LOCK output signal is

asserted when the DLL is locked. Figure 2-5 shows the DLL block diagram and Table 2-5 provides a description of

the DLL inputs and outputs.

The user can configure the DLL for many common functions such as time reference delay mode and clock injection

removal mode. Lattice provides primitives in its design tools for these functions.

Figure 2-5. Delay Locked Loop Diagram (DLL)

CLKOP

CLKOS

LOCK

CLKFB

CLKI

ALUHOLD

DCNTL[5:0]*

GRAYO[5:0]

INCO

UDDCNTL

Phase

Detector

Delay3

Delay2

Delay1

Delay0

Delay4

Reference

Feedback

÷4

÷2

÷4

÷2

RSTN

(from routing

or external pin)

from CLKOP (DLL

internal), from clock net

(CLKOP) or from a user

clock (pin or logic)

Arithmetic

Logic Unit

Lock

Detect

Digital

Control

Output

Delay Chain

Output

Muxes

Duty

Cycle

50%

Duty

Cycle

50%

INCI

GRAYI[5:0]

DIFF

* This signal is not user accessible. This can only be used to feed the slave delay line.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

es) from routing fl and/or division by 2 or by A DLL via CiB. bus from another DLL in lime reference mode TL is difference than the internal selling and updale is needed. er DLLs via CIB. bus to other DLLs via CiB d lour Slave Delay lines, lwo per DLL. The DLLs are in me lowesl Each DLL replaces one EBR block. One Slave Delay line is plac ave Delay line (in Figure 276) for the DLL is placed in the l/O ring b ave Delay lines are fed lo the clock dislribulion nelwork. e see TN117B, LaniceECPQ sysCLQCK PLLzDLL DeSign and Usage Guide Block Diagram, High-Speed DLL and Slave Delay Line HOLD GRMLWEN INCJN RSTN GSRN UDDCNTL DcPaso TPIOO (L) on TPIOT (R) GPLLiPIO ClE (DATA) ClE (CLK) G DLLiPIO Top ECLKI (L) on Tap ECLKZ (H) FB ClE (CLK) internal from CLKOP GDLLFﬁiPIO ECLKl

2-9

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

Table 2-5. DLL Signals

LatticeECP3 devices have two general DLLs and four Slave Delay lines, two per DLL. The DLLs are in the lowest

EBR row and located adjacent to the EBR. Each DLL replaces one EBR block. One Slave Delay line is placed adja-

cent to the DLL and the duplicate Slave Delay line (in Figure 2-6) for the DLL is placed in the I/O ring between

Banks 6 and 7 and Banks 2 and 3.

The outputs from the DLL and Slave Delay lines are fed to the clock distribution network.

For more information, please see TN1178, LatticeECP3 sysCLOCK PLL/DLL Design and Usage Guide.

Figure 2-6. Top-Level Block Diagram, High-Speed DLL and Slave Delay Line

Signal I/O Description

CLKI I Clock input from external pin or routing

CLKFB I DLL feed input from DLL output, clock net, routing or external pin

RSTN I Active low synchronous reset

ALUHOLD I Active high freezes the ALU

UDDCNTL I Synchronous enable signal (hold high for two cycles) from routing

CLKOP O The primary clock output

CLKOS O The secondary clock output with fine delay shift and/or division by 2 or by 4

LOCK O Active high phase lock indicator

INCI I Incremental indicator from another DLL via CIB.

GRAYI[5:0] I Gray-coded digital control bus from another DLL in time reference mode.

DIFF O Difference indicator when DCNTL is difference than the internal setting and update is needed.

INCO O Incremental indicator to other DLLs via CIB.

GRAYO[5:0] O Gray-coded digital control bus to other DLLs via CIB

CLKOP

CLKOS

LOCK

GRAY_OUT[5:0]

INC_OUT

DIFF

DCNTL[5:0]*

CLKO (to edge clock

muxes as CLKINDEL)

Slave Delay Line

LatticeECP3

High-Speed DLL

DCNTL[5:0]

CLKI

HOLD

GRAY_IN[5:0]

INC_IN

RSTN

GSRN

UDDCNTL

DCPS[5:0]

TPIO0 (L) OR TPIO1 (R)

GPLL_PIO

CIB (DATA)

CIB (CLK)

GDLL_PIO

Top ECLK1 (L) OR Top ECLK2 (R)

FB CIB (CLK)

Internal from CLKOP

GDLLFB_PIO

ECLK1

CLKFB

CLKI

* This signal is not user accessible. It can only be used to feed the slave delay line.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

ta lor source synchronous inputs. PLLs us interfaces. Cascading PLL and DLL nd PLLs. al documentation at the end of this data sheet. LLs, arranged in quadrants. Ila PLL and a DLL are next Figure 277. DLLs in LamerCPS Devices PLL DLL DLLjio 1:} Note Not every PLL has an assomaled DLL I'S evices have two clock dividers, one on the |ef1 side and one on the righ o generate a slowerrspeed system clock from a high-speed edge cio and maintains a known phase relationship between the divide d on the release 01 its reset signal. The clock dividers can be led 1r lines, routing or lrom an external clock input. The clock diVide ed into the clock distribution network. The Reset (HST) control 5 puts to low. The RELEASE signal releases outputs synchron clock dividers, please see TN117B, LatticeECPS sysCLOCK PLIJDLL Design and Usage Guide the clock divider connections.

2-10

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

PLL/DLL Cascading

LatticeECP3 devices have been designed to allow certain combinations of PLL and DLL cascading. The allowable

combinations are:

• PLL to PLL supported

• PLL to DLL supported

The DLLs in the LatticeECP3 are used to shift the clock in relation to the data for source synchronous inputs. PLLs

are used for frequency synthesis and clock generation for source synchronous interfaces. Cascading PLL and DLL

blocks allows applications to utilize the unique benefits of both DLLs and PLLs.

For further information about the DLL, please see the list of technical documentation at the end of this data sheet.

PLL/DLL PIO Input Pin Connections

All LatticeECP3 devices contains two DLLs and up to ten PLLs, arranged in quadrants. If a PLL and a DLL are next

to each other, they share input pins as shown in the Figure 2-7.

Figure 2-7. Sharing of PIO Pins by PLLs and DLLs in LatticeECP3 Devices

Clock Dividers

LatticeECP3 devices have two clock dividers, one on the left side and one on the right side of the device. These are

intended to generate a slower-speed system clock from a high-speed edge clock. The block operates in a ÷2, ÷4 or

÷8 mode and maintains a known phase relationship between the divided down clock and the high-speed clock

based on the release of its reset signal. The clock dividers can be fed from selected PLL/DLL outputs, the Slave

Delay lines, routing or from an external clock input. The clock divider outputs serve as primary clock sources and

feed into the clock distribution network. The Reset (RST) control signal resets input and asynchronously forces all

outputs to low. The RELEASE signal releases outputs synchronously to the input clock. For further information on

clock dividers, please see TN1178, LatticeECP3 sysCLOCK PLL/DLL Design and Usage Guide. Figure 2-8 shows

the clock divider connections.

PLL

DLL

DLL_PIO

PLL_PIO

Note: Not every PLL has an associated DLL.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

Mi i i 4, +2 +4 4» > 4. +5 ed primary clocks and eight secondary clock/control sources. Two n the top, ieﬂ, and right edges of the dewce to support high speed d from external I/Os, the sysCLOCK PLLs, DLLs or routing. These ock distribution system. from six primary source types: PLL outputs, DLL outputs, CLKDIV o SEFiDES Quads. LatticeECPs devices have two to ten sysCLO nd right sides of the device. There are six dedicated clock inputs: two 0 two on the right side of the dewce. Figures 279, 2710 and 2-11 show th 3. mary Clock Sources for LatticeECP3-17 mm mm mm mm Primary Cluck m Elghl an. mm mm cm invm ._<1:e><1:e cu="" m="" u="" .i?="" m="" mm="" m="" mm="" w="">

2-11

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

Figure 2-8. Clock Divider Connections

Clock Distribution Network

LatticeECP3 devices have eight quadrant-based primary clocks and eight secondary clock/control sources. Two

high performance edge clocks are available on the top, left, and right edges of the device to support high speed

interfaces. These clock sources are selected from external I/Os, the sysCLOCK PLLs, DLLs or routing. These clock

sources are fed throughout the chip via a clock distribution system.

Primary Clock Sources

LatticeECP3 devices derive clocks from six primary source types: PLL outputs, DLL outputs, CLKDIV outputs, ded-

icated clock inputs, routing and SERDES Quads. LatticeECP3 devices have two to ten sysCLOCK PLLs and two

DLLs, located on the left and right sides of the device. There are six dedicated clock inputs: two on the top side, two

on the left side and two on the right side of the device. Figures 2-9, 2-10 and 2-11 show the primary clock sources

for LatticeECP3 devices.

Figure 2-9. Primary Clock Sources for LatticeECP3-17

RST

RELEASE

÷1

÷2

÷4

÷8

ECLK2

CLKOP (PLL)

CLKOP (DLL)

ECLK1

CLKDIV

Primary Clock Sources

to Eight Quadrant Clock Selection

From Routing

PLL

DLL

PLL Input

Note: Clock inputs can be configured in differential or single-ended mode.

DLL Input

CLK

DIV

SERDES

Quad

Clock

Input

Clock

Input

PLL Input

DLL Input

Clock

Input

Clock

Input

Clock Input Clock Input

PLL

DLL

CLK

DIV

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

mwm PLLwM cm hum cm mom DLwal PLthwl mwm 365% w l Mum Huuluvg x mm, W w mugm mdmennlm ur smg‘s unded mode rces for LaniceECPS-m, -95, -150 WWW $15. 39E? Primary Cluck m m Eight Quadvam c m E m 5% Q??? grew election 4 I I vu ‘ I mm Sims l l { I I { ' I 225% E D“ D D g

2-12

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

Figure 2-10. Primary Clock Sources for LatticeECP3-35

Figure 2-11. Primary Clock Sources for LatticeECP3-70, -95, -150

Primary Clock Sources

to Eight Quadrant Clock Selection

From Routing

PLL

DLL

PLL Input

DLL Input

CLK

DIV

Clock

Input

Clock

Input

PLL Input

DLL Input

Clock

Input

Clock

Input

Clock Input Clock Input

PLL

DLL

CLK

DIV

SERDES

Quad

Note: Clock inputs can be configured in differential or single-ended mode.

Primary Clock Sources

to Eight Quadrant Clock Selection

From Routing

PLL

DLL

PLL Input

DLL Input

CLK

DIV

Clock

Input

Clock

Input

PLL Input

DLL Input

Clock

Input

Clock

Input

Clock Input Clock Input

PLL

PLL Input PLL Input

PLL

PLL Input PLL Input

PLL

PLL Input PLL Input

PLL

DLL

CLK

DIV

SERDES

Quad

SERDES

Quad

SERDES

Quad

SERDES

Quad

(ECP3-150 only)

Note: Clock inputs can be configured in differential or single-ended mode.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

devtce. All the clock sources Each quadrant mux lS identir EHDES Quads WWWWWwwwww cc Dcc Dcs ocs mary Clocks tCLKD to cum per Quadrant (DOC) ole/Disable) feature allows internal logic control of the quadrant k is disabled, all the logic fed by that clock does not toggle, reducing device. Select (DCS) mart multiplexer function available in the primary clock routing. lt switc ock sources without any glitches or runt pulses. This is achieved regard re are two DCS blocks per quadrant; in total, there are eight DOS D block come from the center muxes. The output of the D08 is conne Figure 2712). gure 2713 shows the timing waveforms of the default DCS ope to other modes. For more information about the DOS, please se this data sheet. Figure 2-13. DOS Waveforms

2-13

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

Primary Clock Routing

The purpose of the primary clock routing is to distribute primary clock sources to the destination quadrants of the

device. A global primary clock is a primary clock that is distributed to all quadrants. The clock routing structure in

LatticeECP3 devices consists of a network of eight primary clock lines (CLK0 through CLK7) per quadrant. The pri-

mary clocks of each quadrant are generated from muxes located in the center of the device. All the clock sources

are connected to these muxes. Figure 2-12 shows the clock routing for one quadrant. Each quadrant mux is identi-

cal. If desired, any clock can be routed globally.

Figure 2-12. Per Quadrant Primary Clock Selection

Dynamic Clock Control (DCC)

The DCC (Quadrant Clock Enable/Disable) feature allows internal logic control of the quadrant primary clock net-

work. When a clock network is disabled, all the logic fed by that clock does not toggle, reducing the overall power

consumption of the device.

Dynamic Clock Select (DCS)

The DCS is a smart multiplexer function available in the primary clock routing. It switches between two independent

input clock sources without any glitches or runt pulses. This is achieved regardless of when the select signal is tog-

gled. There are two DCS blocks per quadrant; in total, there are eight DCS blocks per device. The inputs to the

DCS block come from the center muxes. The output of the DCS is connected to primary clocks CLK6 and CLK7

(see Figure 2-12).

Figure 2-13 shows the timing waveforms of the default DCS operating mode. The DCS block can be programmed

to other modes. For more information about the DCS, please see the list of technical documentation at the end of

this data sheet.

Figure 2-13. DCS Waveforms

CLK0 CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 CLK7

63:1 63:1 63:1 63:1 58:1 58:1 58:1 58:163:1 63:1

DCC DCC DCC DCC DCS DCSDCC DCC

8 Primary Clocks (CLK0 to CLK7) per Quadrant

PLLs + DLLs + CLKDIVs + PCLK PIOs + SERDES Quads

CLK0

SEL

DCSOUT

CLK1

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

TY c |npu| $$YY From Ranking From Routing YT ii From From Routing Routing Note Clock inputs can be mnligured in Secondary Clock/Control Rou Global secondary clock is a seconda routing is to distribute the sec LatticeECPa dewces are region dihon to 8007803, 807 is also an along with 804607. High lanout logic e inputs to X2 switches, and SCAVSC7 n also access control signals CE/LSFl. From From Routing Routing From Routing From Routing 11: Secondary Clock Sources ii%% 11

2-14

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

Secondary Clock/Control Sources

LatticeECP3 devices derive eight secondary clock sources (SC0 through SC7) from six dedicated clock input pads

and the rest from routing. Figure 2-14 shows the secondary clock sources. All eight secondary clock sources are

defined as inputs to a per-region mux SC0-SC7. SC0-SC3 are primary for control signals (CE and/or LSR), and

SC4-SC7 are for clock and high fanout data.

In an actual implementation, there is some overlap to maximize routability. In addition to SC0-SC3, SC7 is also an

input to the control signals (LSR or CE). SC0-SC2 are also inputs to clocks along with SC4-SC7. High fanout logic

signals (LUT inputs) will utilize the X2 and X0 switches where SC0-SC7 are inputs to X2 switches, and SC4-SC7

are inputs to X0 switches. Note that through X0 switches, SC4-SC7 can also access control signals CE/LSR.

Figure 2-14. Secondary Clock Sources

Secondary Clock/Control Routing

Global secondary clock is a secondary clock that is distributed to all regions. The purpose of the secondary clock

routing is to distribute the secondary clock sources to the secondary clock regions. Secondary clocks in the

LatticeECP3 devices are region-based resources. Certain EBR rows and special vertical routing channels bind the

secondary clock regions. This special vertical routing channel aligns with either the left edge of the center DSP

slice in the DSP row or the center of the DSP row. Figure 2-15 shows this special vertical routing channel and the

20 secondary clock regions for the LatticeECP3 family of devices. All devices in the LatticeECP3 family have eight

Secondary Clock Sources

From Routing

From

Routing

From

Routing

From

Routing

From

Routing

From

Routing

From

Routing

From

Routing

From

Routing

From Routing

Clock Input

Clock

Input

Clock

Input

Clock Input

From Routing

Note: Clock inputs can be configured in differential or single-ended mode.

From Routing

Clock Input

From Routing

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

ndary Clock Regions Vemcal Rouiing 0nannei Regional Boundary ‘ ‘ /e/yslo Bank1 ‘ 7 _ - _ ‘ _ ‘c‘ é / EBR Row ary 01ock Secondary 01ock Secondary 01ock g " Reglonal Boundary gion R102 Region R103 I Region R104 ‘ Pg“ ' 5v _ _ _ _ 4. _ /| E I 0 00k Secondary 01ock Secondary 01ock I Secondary 01oek | i n R201 Region R202 Region R203 Region R204 i - .. J _ _ _ _ | l i Secondary 01ock I Secondary 01ock Secondary 01ock I Secondary 01o ﬂ Region R301 Region R302 Region R303 I Region R304 Secondary 01ock | Secondary 01ock Secondary 01ock i In Region R401 Region R402 I Region R403 i I ' 3 _ _ - _ _ _ 9 I 3 vi h Secondary Ciook Secondary ciock Seco 00k En _ Region R501 Region R502 Re 04 o ‘ SERDES

2-15

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

secondary clock resources per region (SC0 to SC7). The same secondary clock routing can be used for control

signals.

Table 2-6. Secondary Clock Regions

Figure 2-15. LatticeECP3-70 and LatticeECP3-95 Secondary Clock Regions

Device

Number of Secondary Clock

Regions

ECP3-17 16

ECP3-35 16

ECP3-70 20

ECP3-95 20

ECP3-150 36

sysIO Bank 0 sysIO Bank 1

SERDES

sysIO Bank 7

sysIO Bank 2

sysIO Bank 6

sysIO Bank 3 Configuration Bank

Secondary Clock

Region R1C1

Secondary Clock

Region R2C1

Secondary Clock

Region R3C1

Secondary Clock

Region R4C1

Secondary Clock

Region R5C1

Secondary Clock

Region R1C2

Secondary Clock

Region R2C2

Secondary Clock

Region R3C2

Secondary Clock

Region R4C2

Secondary Clock

Region R5C2

Secondary Clock

Region R1C3

Vertical Routing Channel

Regional Boundary

Secondary Clock

Region R2C3

Secondary Clock

Region R3C3

Secondary Clock

Region R4C3

Secondary Clock

Region R5C3

Secondary Clock

Region R1C4

Secondary Clock

Region R2C4

Secondary Clock

Region R3C4

Secondary Clock

Region R4C4

Secondary Clock

Region R5C4

EBR Row

Regional Boundary

EBR Row

Regional Boundary

Spine Repeaters

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

sue sc7 er Hegmn k/Conlvm gure 2718 shows the comrol seXecmns 1or S‘iceo xhrough Shcez. AH ocks are routed to this dock selection mux. Other signals can be g. Shce comrols are generaked from me secondary clocks/conxrols for both clock and comrol men the de1aun value of me mux ompui erefore n does not have the clock or comrol muxes. ugh Slice2 Clock Selection Primary Clock 5 Secondary Clock 7 mm .0 s Rouhng 12 Van: Figure 2-18. Slice!) through Slicez Control Selection Secondary c

2-16

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

Figure 2-16. Per Region Secondary Clock Selection

Slice Clock Selection

Figure 2-17 shows the clock selections and Figure 2-18 shows the control selections for Slice0 through Slice2. All

the primary clocks and seven secondary clocks are routed to this clock selection mux. Other signals can be used

as a clock input to the slices via routing. Slice controls are generated from the secondary clocks/controls or other

signals connected via routing.

If none of the signals are selected for both clock and control then the default value of the mux output is 1. Slice 3

does not have any registers; therefore it does not have the clock or control muxes.

Figure 2-17. Slice0 through Slice2 Clock Selection

Figure 2-18. Slice0 through Slice2 Control Selection

SC0 SC1 SC2 SC3 SC4 SC5

8:1 8:1 8:1 8:1

SC6

8:1

SC7

8:18:1 8:1

8 Secondary Clocks (SC0 to SC7) per Region

Clock/Control

Secondary Clock Feedlines: 8 PIOs + 16 Routing

Clock to Slice

Primary Clock

Secondary Clock

Routing

Vcc

28:1

Slice Control

Secondary Control

Routing

Vcc

20:1

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

1 1 1 1 1 1 1 1 Sources ior up 1 1 edgeclocks 777777777777777777 11 1 ﬁﬁeeeﬁﬁﬁﬁﬁee 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4—{me Roui1ng1 1 1 1 1 1 1 1 Clock 1 1 1 1 1npu1 1 1 1 1 Ciock 1 1 1 1 Inpui 1 1 1 1 1 }—. 1 Six Edge Clocks (ECLK) 1 4—{F1om m 1 1 1 1:1_. 1 Two Clocks per Edge 1 1 1 1 e 1 1 W31 1« “<33 1="" 1="" 1="" 1="" 1="" 1="" 1="" 1="" k="" 1="" 1="" 4="" 1="" 1="" 1="" 1="" a="" 1="" 1="" f="" 1="" 1="" 1="" 1="" 1="" 1="" 1="" 1="" 1="" 1="" 11="" edge="" clocks="" 1="" 1="" 1="" 1="" 1="" 1="" 1="" l="" 77777777777777777="" 1="" l="" ,,,,,,,,,,,,,,,,,="" j="" 0155="" clock="" 1npuis="" can="" be="" canhguved="" m="" d1ffevamial="" or="" sing1e="" ended="" made="" the="" two="" dlls="" can="" also="" drive="" me="" two="" 10p="" edge="" ciucks="" a.="" the="" lap="" leﬂ="" and="" lap="" "gm="" pll="" can="" a1so="" dnve="" me="" we="" iop="" edge="" clocks.="" edge="" clock="" homing="" lamceecpa="" devices="" have="" a="" number="" 01="" highrspeed="" edge="" implememaiion="" of="" highrspeed="" inierfaces.="" there="" are="" 51="" ieﬂ,="" and="" righi="" edges.="" diﬂereni="" pll="" and="" dll="" ouiputs="" a="" device.="" in="" addition,="" ihe="" clkindel="" signal="" (gener="" clock="" muxes="" on="" the="" leii="" and="" right="" sides="" of="" me="" dev="">

2-17

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

Edge Clock Sources

Edge clock resources can be driven from a variety of sources at the same edge. Edge clock resources can be

driven from adjacent edge clock PIOs, primary clock PIOs, PLLs, DLLs, Slave Delay and clock dividers as shown in

Figure 2-19.

Figure 2-19. Edge Clock Sources

Edge Clock Routing

LatticeECP3 devices have a number of high-speed edge clocks that are intended for use with the PIOs in the

implementation of high-speed interfaces. There are six edge clocks per device: two edge clocks on each of the top,

left, and right edges. Different PLL and DLL outputs are routed to the two muxes on the left and right sides of the

device. In addition, the CLKINDEL signal (generated from the DLL Slave Delay Line block) is routed to all the edge

clock muxes on the left and right sides of the device. Figure 2-20 shows the selection muxes for these clocks.

Six Edge Clocks (ECLK)

Two Clocks per Edge

Sources for right edge clocks

Clock

Input

Clock

Input

From Routing

From

Routing

From

Routing

Clock Input Clock Input

From Routing

Clock

Input

Clock

Input

From Routing

Sources for left edge clocks

Notes:

1. Clock inputs can be configured in differential or single ended mode.

2. The two DLLs can also drive the two top edge clocks.

3. The top left and top right PLL can also drive the two top edge clocks.

Sources for top

edge clocks

DLL

Input

PLL

Input

DLL

Input

PLL

Input

Slave Delay

DLL

PLL

DLL

PLL

Slave Delay

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

M M Le“ and mm Edge (Necks ECLK2 6:1 4r M m CLKOS 4H Rouhng 4b CLKINDEL 4b m DLL Slave Delay dge Clock (Top Edge) Input Pad Top len PLL7CLKOP Top Rxghl PLLJJLKOS Len DLL,CLKOP Rxgm DLLJJLKOS Homing CLKINDEL (Leﬂ DLLiDEL) ECLK1 7,1 4» MML Inpm Pad Top mgm PLLJJLKOP Top Len PLLJ: Rxgm Leﬂ Milli l

2-18

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

Figure 2-20. Sources of Edge Clock (Left and Right Edges)

Figure 2-21. Sources of Edge Clock (Top Edge)

The edge clocks have low injection delay and low skew. They are used to clock the I/O registers and thus are ideal

for creating I/O interfaces with a single clock signal and a wide data bus. They are also used for DDR Memory or

Generic DDR interfaces.

Left and Right

Edge Clocks

ECLK1

Routing

Input Pad

PLL Input Pad

DLL Output CLKOP

PLL Output CLKOP

CLKINDEL

from DLL Slave Delay

Left and Right

Edge Clocks

ECLK2

Routing

Input Pad

PLL Input Pad

DLL Output CLKOS

PLL Output CLKOS

CLKINDEL

from DLL Slave Delay

6:1

ECLK1

ECLK2

Input Pad

Top left PLL_CLKOP

Routing

CLKINDEL

Top Right PLL_CLKOS

Left DLL_CLKOP

Right DLL_CLKOS

(Left DLL_DEL)

Input Pad

Top Right PLL_CLKOP

Routing

CLKINDEL

Top Left PLL_CLKOS

Right DLL_CLKOP

Left DLL_CLKOS

(Right DLL_DEL)

7:1

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

EBR consists of an 18*Kbit arate clock and clock enable. Each glerpori RAM, ROM and FIFO buffers udo dual port memories. Each block can be used in an be implemented in sysMEM EBR blocks by implev s parity checking by supporting an optional parity bit tor for conﬁgurations with187oit and Gerbil data widths. For , LatticeECPS Memory Usage Guide. ory Mode Configurations 16‘384x1 8,192x2 4‘096X4 2,048x9 1‘024x 18 512 x36 16884 x 1 8192 x 2 True Dual Port 41096 x A 2,048 x 9 1024 x 18 16,384x1 8192 x 2 4‘096x4 2‘048x9 1‘024x 18 51 Single Port Pseudo Dual Port Bus Size Matching All of the multirport memory modes support diﬂerent Width word 0 to MSB word 0, LSB word 1 to MSB word 1, and s each port varies, this mapping scheme applies to eac FlAM Initialization and ROM Operation If desired, the contents of the RAM can be me during the chip configuration cycle and dis ROM. Memory Cascading Larger and deeper blocks of RA cascade memory transparently,

2-19

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

The edge clocks on the top, left, and right sides of the device can drive the secondary clocks or general routing

resources of the device. The left and right side edge clocks also can drive the primary clock network through the

clock dividers (CLKDIV).

sysMEM Memory

LatticeECP3 devices contain a number of sysMEM Embedded Block RAM (EBR). The EBR consists of an 18-Kbit

RAM with memory core, dedicated input registers and output registers with separate clock and clock enable. Each

EBR includes functionality to support true dual-port, pseudo dual-port, single-port RAM, ROM and FIFO buffers

(via external PFUs).

sysMEM Memory Block

The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in

a variety of depths and widths as shown in Table 2-7. FIFOs can be implemented in sysMEM EBR blocks by imple-

menting support logic with PFUs. The EBR block facilitates parity checking by supporting an optional parity bit for

each data byte. EBR blocks provide byte-enable support for configurations with18-bit and 36-bit data widths. For

more information, please see TN1179, LatticeECP3 Memory Usage Guide.

Table 2-7. sysMEM Block Configurations

Bus Size Matching

All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB

word 0 to MSB word 0, LSB word 1 to MSB word 1, and so on. Although the word size and number of words for

each port varies, this mapping scheme applies to each port.

RAM Initialization and ROM Operation

If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block

during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a

ROM.

Memory Cascading

Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools

cascade memory transparently, based on specific design inputs.

Memory Mode Configurations

Single Port

16,384 x 1

8,192 x 2

4,096 x 4

2,048 x 9

1,024 x 18

512 x 36

True Dual Port

16,384 x 1

8,192 x 2

4,096 x 4

2,048 x 9

1,024 x 18

Pseudo Dual Port

16,384 x 1

8,192 x 2

4,096 x 4

2,048 x 9

1,024 x 18

512 x 36

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

operation: e cycle, the daia (a1 the current daia widths. ame pori during a write cycle. This rlen, ihe old content ol the address appears at a Widths. A and B output ports. These latches can be reset asynchror signals, which resei the output latches assocrated with Port A FiN) signal can reset both ports. The output data latches and assor ure 2722. l ******** l Msmnw Core 1 o i Pan Amza] l l ﬁ—b Lcm ‘ l l l l 1 Output Data ‘ ‘ Latches 1 l Port l l RSTA wﬂi RSTB |:l> ) GSRN wﬂjf l —Programmable Disable For further information on ihe sysMEM EBR block, ple data sheet. sysDSP‘"I Slice The LatticeECPa family provides an enhan lormance Digital Signal Processing (DSP Impulse Response (FIR) filters, Fast F lution encoders and decoders. These tiplyradders and multiplyraccum

2-20

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

Single, Dual and Pseudo-Dual Port Modes

In all the sysMEM RAM modes the input data and address for the ports are registered at the input of the memory

array. The output data of the memory is optionally registered at the output.

EBR memory supports the following forms of write behavior for single port or dual port operation:

1. Normal – Data on the output appears only during a read cycle. During a write cycle, the data (at the current

address) does not appear on the output. This mode is supported for all data widths.

2. Write Through – A copy of the input data appears at the output of the same port during a write cycle. This

mode is supported for all data widths.

3. Read-Before-Write (EA devices only) – When new data is written, the old content of the address appears at

the output. This mode is supported for x9, x18, and x36 data widths.

Memory Core Reset

The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchro-

nously or synchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A

and Port B, respectively. The Global Reset (GSRN) signal can reset both ports. The output data latches and asso-

ciated resets for both ports are as shown in Figure 2-22.

Figure 2-22. Memory Core Reset

For further information on the sysMEM EBR block, please see the list of technical documentation at the end of this

data sheet.

sysDSP™ Slice

The LatticeECP3 family provides an enhanced sysDSP architecture, making it ideally suited for low-cost, high-per-

formance Digital Signal Processing (DSP) applications. Typical functions used in these applications are Finite

Impulse Response (FIR) filters, Fast Fourier Transforms (FFT) functions, Correlators, Reed-Solomon/Turbo/Convo-

lution encoders and decoders. These complex signal processing functions use similar building blocks such as mul-

tiply-adders and multiply-accumulators.

sysDSP Slice Approach Compared to General DSP

Conventional general-purpose DSP chips typically contain one to four (Multiply and Accumulate) MAC units with

fixed data-width multipliers; this leads to limited parallelism and limited throughput. Their throughput is increased by

higher clock speeds. The LatticeECP3, on the other hand, has many DSP slices that support different data widths.

SET

CLR

Output Data

Latches

Memory Core

Port A[17:0]

SET

DPort B[17:0]

RSTB

GSRN

Programmable Disable

RSTA

CLR

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

,, Operand B m/k loops Mulllpller k m/k accumulate Function Implemented ln Lameeecpa sysDSP Slice Architecture Features P3 sysDSP Slice has been significantly enhanced to provide functio plicatlons. These enhancements provide improved ﬂexibility and res atticeECP3 sysDSP Slice supports many functions that include the Multiply (one 18x36, two 18x18 or four 9x9 Multiplies per Slice) Multiply (36x36 by cascading across two sysDSP slices) Multiply Accumulate (up to 18x36 Multipliers feeding a Two Multiplies feeding one Accumulate per cycle for in tiplies feed into an accumulator that can accumu Flexible saturation and rounding options to Flexible cascading across DSP slices , Minimizes fabric use for common D , Enables implementation of HR FlIte , Provides matching pipeline re , Can be configured to continue chains

2-21

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

This allows designers to use highly parallel implementations of DSP functions. Designers can optimize DSP perfor-

mance vs. area by choosing appropriate levels of parallelism. Figure 2-23 compares the fully serial implementation

to the mixed parallel and serial implementation.

Figure 2-23. Comparison of General DSP and LatticeECP3 Approaches

LatticeECP3 sysDSP Slice Architecture Features

The LatticeECP3 sysDSP Slice has been significantly enhanced to provide functions needed for advanced pro-

cessing applications. These enhancements provide improved flexibility and resource utilization.

The LatticeECP3 sysDSP Slice supports many functions that include the following:

• Multiply (one 18x36, two 18x18 or four 9x9 Multiplies per Slice)

• Multiply (36x36 by cascading across two sysDSP slices)

• Multiply Accumulate (up to 18x36 Multipliers feeding an Accumulator that can have up to 54-bit resolution)

• Two Multiplies feeding one Accumulate per cycle for increased processing with lower latency (two 18x18 Mul-

tiplies feed into an accumulator that can accumulate up to 52 bits)

• Flexible saturation and rounding options to satisfy a diverse set of applications situations

• Flexible cascading across DSP slices

– Minimizes fabric use for common DSP and ALU functions

– Enables implementation of FIR Filter or similar structures using dedicated sysDSP slice resources only

– Provides matching pipeline registers

– Can be configured to continue cascading from one row of sysDSP slices to another for longer cascade

chains

• Flexible and Powerful Arithmetic Logic Unit (ALU) Supports:

– Dynamically selectable ALU OPCODE

– Ternary arithmetic (addition/subtraction of three inputs)

– Bit-wise two-input logic operations (AND, OR, NAND, NOR, XOR and XNOR)

– Eight flexible and programmable ALU flags that can be used for multiple pattern detection scenarios, such

Multiplier

xx x

Multiplier

(k adds)

Output

Single

Multiplier x

Operand

Accumulator

M loops

Function Implemented in

General Purpose DSP

Function Implemented in

LatticeECP3

m/k

accumulate

m/k

loops

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

rapplicaﬁons thak require e is backwardsrcompanble with me d m Ihe LamceECPa sysDSP slice. The wo adjacent LamceECPS sysDSP s‘ices, as PGA Core I Sllce 1 *4 H Hmmwm il* 74 ‘—>‘ %a\ m M m ‘—~ ‘9x9‘ ‘9x9 ““9x9‘ ‘9x9 ‘1 1 H ‘ii‘m‘ ‘9x9‘1 ‘ ‘ x H Onenﬁ 1‘ “1‘ Mulnﬂ-I ‘1 1‘ MuIHB-O ‘11‘ Mum-1 ‘1 "‘35? ‘ PH ‘ ‘ PH ‘ ‘ pH ‘ ‘ FR ‘ ——°337 ——°0 ““33“” Reg R H 1pm Regxslers on on on on on on GR To FPGA Care

2-22

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

as, overflow, underflow and convergent rounding, etc.

– Flexible cascading across slices to get larger functions

• RTL Synthesis friendly synchronous reset on all registers, while still supporting asynchronous reset for legacy

users

• Dynamic MUX selection to allow Time Division Multiplexing (TDM) of resources for applications that require

processor-like flexibility that enables different functions for each clock cycle

For most cases, as shown in Figure 2-24, the LatticeECP3 DSP slice is backwards-compatible with the

LatticeECP2™ sysDSP block, such that, legacy applications can be targeted to the LatticeECP3 sysDSP slice. The

functionality of one LatticeECP2 sysDSP Block can be mapped into two adjacent LatticeECP3 sysDSP slices, as

shown in Figure 2-25.

Figure 2-24. Simplified sysDSP Slice Block Diagram

PR PR

MULTA MULTAMULTB MULTB

Mult18-0 Mult18-0 Mult18-1

One of

these

Mult18-1

OR OR

Input Registers

from SRO of

Left-side DSP

ALU Op-Codes

Slice 0 Slice 1

Cascade from

Left DSP Accumulator/ALU (54) Accumulator/ALU (54)

To FPGA Core

From FPGA Core

Cascade to

Right DSP

Intermediate Pipeline

Registers

Output Registers OR OR OR OR OR OR

Carry

Out

Reg.

Carry

Out

Reg.

9x9 9x9 9x9 9x9 9x9 9x9 9x9 9x9

Casc

A0 Casc

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

Next DSP Slice R:A:E:C R:Logic(B.C) Tn FPGA Core LU and CiALU are internal Signals generated by cumblnlng bils lmm AA, AB, BA BB and c 32, LauiceECFQ sysDSP Usage Guide lor lurmer lnlurmallun 2 sysDSP block supports the lollowing basic elements. Multiply) (Multiply, Accumulate) MULTADDSUB (Multiply, Addition/Subtraction) MULTADDSUBSUM (Multiply, Addition/Sublramion, Summati Table 278 shows the capabilities 01 each 01 the Lat‘liceECPS slice Table 2-8. Maximum Number of Elements in 5 Slice Width ol Multiply x9 MULT 4 MAC 1 MULTADDSUB MULTADDSUBSUM 1. One Slice can implement 1/2 9x9 Some options are available in th be loaded as a shift register from

2-23

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

Figure 2-25. Detailed sysDSP Slice Diagram

The LatticeECP2 sysDSP block supports the following basic elements.

• MULT (Multiply)

• MAC (Multiply, Accumulate)

• MULTADDSUB (Multiply, Addition/Subtraction)

• MULTADDSUBSUM (Multiply, Addition/Subtraction, Summation)

Table 2-8 shows the capabilities of each of the LatticeECP3 slices versus the above functions.

Table 2-8. Maximum Number of Elements in a Slice

Some options are available in the four elements. The input register in all the elements can be directly loaded or can

be loaded as a shift register from previous operand registers. By selecting “dynamic operation” the following opera-

tions are possible:

• In the Add/Sub option the Accumulator can be switched between addition and subtraction on every cycle.

• The loading of operands can switch between parallel and serial operations.

Width of Multiply x9 x18 x36

MULT 4 2 1/2

MAC 1 1 —

MULTADDSUB 2 1 —

MULTADDSUBSUM 111/2 —

1. One slice can implement 1/2 9x9 m9x9addsubsum and two m9x9addsubsum with two slices.

R= A ± B ± C

R = Logic (B, C)

AA AB BA BB

MULTA MULTB

BMUX

AMUX

CMUX

ALU

A_ALU B_ALU

PRPR

Rounding

A_ALU

OPCODEC

CIN COUT

SROB

SROA

SRIB

SRIA

C_ALU

From FPGA Core

To FPGA Core

IR = Input Register

PR = Pipeline Register

OR = Output Register

FR = Flag Register

Note: A_ALU, B_ALU and C_ALU are internal signals generated by combining bits from AA, AB, BA BB and C

inputs. See TN1182, LatticeECP3 sysDSP Usage Guide, for further information.

DSP Slice

IR IR IR IR

OROR FR

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

,La 'ceECPS s sDSP Usa e G 'de m/outpm and pipeline regisr SROB ‘R SROA W ‘1 Next DSP Shae mum Regwsler FR = Flag Regwsler new, a me Regws|ev Tn FPGA Cave

2-24

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

For further information, please refer to TN1182, LatticeECP3 sysDSP Usage Guide.

MULT DSP Element

This multiplier element implements a multiply with no addition or accumulator nodes. The two operands, AA and

AB, are multiplied and the result is available at the output. The user can enable the input/output and pipeline regis-

ters. Figure 2-26 shows the MULT sysDSP element.

Figure 2-26. MULT sysDSP Element

R= A ± B ± C

R = Logic (B, C)

AA AB BA BB

MULTA MULTB

BMUX

AMUX

CMUX

ALU

A_ALU B_ALU

PRPR

Rounding

A_ALU

OPCODEC

CIN COUT

SROB

SROA

SRIB

SRIA

C_ALU

From FPGA Core

To FPGA Core

IR = Input Register

PR = Pipeline Register

OR = Output Register

FR = Flag Register

DSP Slice

IR IR IR IR

OROR FR

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

alized dynamically. A regisr Ihis documem. Figure 2727 i i ODE BA BB SROB ‘R SROA Next DSP Shae pm Regwstev wanna negmey on 7 Outpul newer FR = Flag newer Tn FPGA Cave

2-25

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

MAC DSP Element

In this case, the two operands, AA and AB, are multiplied and the result is added with the previous accumulated

value. This accumulated value is available at the output. The user can enable the input and pipeline registers, but

the output register is always enabled. The output register is used to store the accumulated value. The ALU is con-

figured as the accumulator in the sysDSP slice in the LatticeECP3 family can be initialized dynamically. A regis-

tered overflow signal is also available. The overflow conditions are provided later in this document. Figure 2-27

shows the MAC sysDSP element.

Figure 2-27. MAC DSP Element

R= A ± B ± C

R = Logic (B, C)

AA AB BA BB

MULTA MULTB

BMUX

AMUX

CMUX

ALU

A_ALU B_ALU

PR PR

Rounding

A_ALU

OPCODEC

CIN COUT

SROB

SROA

SRIB

SRIA

C_ALU

From FPGA Core

To FPGA Core

IR = Input Register

PR = Pipeline Register

OR = Output Register

FR = Flag Register

DSP Slice

IR IR IR

OROR OR FR

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

enabled. The omput regisxer he sysDSP slice. A regisiered documem. Figure 2728 shows me Next DSP Shae R Pwpehne Regwsler on Ompm newer FR = Hag Heg‘slev Tn FPGA Cave

2-26

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

MMAC DSP Element

The LatticeECP3 supports a MAC with two multipliers. This is called Multiply Multiply Accumulate or MMAC. In this

case, the two operands, AA and AB, are multiplied and the result is added with the previous accumulated value and

with the result of the multiplier operation of operands BA and BB. This accumulated value is available at the output.

The user can enable the input and pipeline registers, but the output register is always enabled. The output register

is used to store the accumulated value. The ALU is configured as the accumulator in the sysDSP slice. A registered

overflow signal is also available. The overflow conditions are provided later in this document. Figure 2-28 shows the

MMAC sysDSP element.

Figure 2-28. MMAC sysDSP Element

R= A ± B ± C

R = Logic (B, C)

AA AB BA BB

MULTA MULTB

BMUX

AMUX

CMUX

ALU

A_ALU B_ALU

Rounding

A_ALU

OPCODEC

CIN COUT

SROB

SROA

SRIB

SRIA

C_ALU

From FPGA Core

To FPGA Core

IR = Input Register

PR = Pipeline Register

OR = Output Register

FR = Flag Register

DSP Slice

IR IR IR IR

OROR FR

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

SROB IR 4» Ev ne Regwslev pm Regwsler ag Regwster MULTE ALU ‘R SROA Tn FPGA Cave Next DSP Shae

2-27

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

MULTADDSUB DSP Element

In this case, the operands AA and AB are multiplied and the result is added/subtracted with the result of the multi-

plier operation of operands BA and BB. The user can enable the input, output and pipeline registers. Figure 2-29

shows the MULTADDSUB sysDSP element.

Figure 2-29. MULTADDSUB

R= A ± B ± C

R = Logic (B, C)

AA AB BA BB

MULTA MULTB

BMUX

AMUX

CMUX

ALU

A_ALU B_ALU

PRPR

Rounding

A_ALU

OPCODEC

CIN COUT

SROB

SROA

SRIB

SRIA

C_ALU

From FPGA Core

To FPGA Core

IR = Input Register

PR = Pipeline Register

OR = Output Register

FR = Flag Register

DSP Slice

IR IR IR IR

ORFROR

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

e path. The user can enable LTADDSUBSUM SysDSP eler \ \ L L is»: as ‘H SHOA COUT 7,H , a To FFGA Cove

2-28

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

MULTADDSUBSUM DSP Element

In this case, the operands AA and AB are multiplied and the result is added/subtracted with the result of the multi-

plier operation of operands BA and BB of Slice 0. Additionally, the operands AA and AB are multiplied and the

result is added/subtracted with the result of the multiplier operation of operands BA and BB of Slice 1. The results

of both addition/subtractions are added by the second ALU following the slice cascade path. The user can enable

the input, output and pipeline registers. Figure 2-30 and Figure 2-31 show the MULTADDSUBSUM sysDSP ele-

ment.

Figure 2-30. MULTADDSUBSUM Slice 0

R= A ± B ± C

R = Logic (B, C)

AA AB BA BB

MULTA MULTB

BMUX

AMUX

CMUX

ALU

A_ALU B_ALU

PR PR

Rounding

A_ALU

OPCODEC

CIN COUT

SROB

SROA

SRIB

SRIA

C_ALU

From FPGA Core

To FPGA Core

IR = Input Register

PR = Pipeline Register

OR = Output Register

FR = Flag Register

DSP Slice

IR IR

OROR OR

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

i F74 F74 4", 0A M A X X Next 05? 5m 443W ’7 4’ : B : c 7 % ALU on i To FFGA Core ice Features SP slice has been enhanced to allow cascading. Adder trees are i g the performance. Cascading of shoes uses the signals CIN, 0 eECP3 sysDSP slice aliows tor the bypassing of multipliers and ca adder iunctions are impiemented without the use of LUTs. The m ted are 54-bit. Rounding The rounding operation is implemented in the ALU and is done b ation. The rounding methods supported are: - Rounding to zero (RTZ) Rounding to inﬁnity (RTI) Dynamic rounding Random rounding Convergent rounding

2-29

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

Figure 2-31. MULTADDSUBSUM Slice 1

Advanced sysDSP Slice Features

Cascading

The LatticeECP3 sysDSP slice has been enhanced to allow cascading. Adder trees are implemented fully in sys-

DSP slices, improving the performance. Cascading of slices uses the signals CIN, COUT and C Mux of the slice.

Addition

The LatticeECP3 sysDSP slice allows for the bypassing of multipliers and cascading of adder logic. High perfor-

mance adder functions are implemented without the use of LUTs. The maximum width adders that can be imple-

mented are 54-bit.

Rounding

The rounding operation is implemented in the ALU and is done by adding a constant followed by a truncation oper-

ation. The rounding methods supported are:

• Rounding to zero (RTZ)

• Rounding to infinity (RTI)

• Dynamic rounding

• Random rounding

• Convergent rounding

R= A ± B ± C

R = Logic (B, C)

AA AB BA BB

MULTA MULTB

BMUX

AMUX

CMUX

ALU

A_ALU B_ALU

PR PR

Rounding

A_ALU

OPCODEC

CIN COUT

SROB

SROA

SRIB

SRIA

C_ALU

From FPGA Core

To FPGA Core

IR = Input Register

PR = Pipeline Register

OR = Output Register

FR = Flag Register

DSP Slice

IR IR

OROR

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

acy designs (OVEFlUNDER) and Reset Resources routing are available to every sysDSP slice. From four clock ock is selected for each input register, pipeline register and output (HST) are selected at each input register, pipeline register and out the LatticeECPS Family er of multipliers for each member of the LatticeECPa family. Table M Blocks in each LatticeECPS device. EBR blocks, together With es locally for last DSP operations. Number of DSP Slices in the LatticeECPS Family DSP Slices 9x9 Multiplier 18x18 Multip 12 48 24 ECPB-BS 32 128 PCS-70 64 256 ECP3-95 64 256 ECP3-150 160 640 ble 2-10. Embedded SHAM in the LatticeECP3 Family Device EBR SRAM ECP3-17 ECPG—SS ECP3-70 ECPS-QS ECP3-150

2-30

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

ALU Flags

The sysDSP slice provides a number of flags from the ALU including:

• Equal to zero (EQZ)

• Equal to zero with mask (EQZM)

• Equal to one with mask (EQOM)

• Equal to pattern with mask (EQPAT)

• Equal to bit inverted pattern with mask (EQPATB)

• Accumulator Overflow (OVER)

• Accumulator Underflow (UNDER)

• Either over or under flow supporting LatticeECP2 legacy designs (OVERUNDER)

Clock, Clock Enable and Reset Resources

Global Clock, Clock Enable and Reset signals from routing are available to every sysDSP slice. From four clock

sources (CLK0, CLK1, CLK2, and CLK3) one clock is selected for each input register, pipeline register and output

put register.

Resources Available in the LatticeECP3 Family

Table 2-9 shows the maximum number of multipliers for each member of the LatticeECP3 family. Table 2-10 shows

the maximum available EBR RAM Blocks in each LatticeECP3 device. EBR blocks, together with Distributed RAM

can be used to store variables locally for fast DSP operations.

Table 2-9. Maximum Number of DSP Slices in the LatticeECP3 Family

Table 2-10. Embedded SRAM in the LatticeECP3 Family

Device DSP Slices 9x9 Multiplier 18x18 Multiplier 36x36 Multiplier

ECP3-17 12 48 24 6

ECP3-35 32 128 64 16

ECP3-70 64 256 128 32

ECP3-95 64 256 128 32

ECP3-150 160 640 320 80

Device EBR SRAM Block

Total EBR SRAM

(Kbits)

ECP3-17 38 700

ECP3-35 72 1327

ECP3-70 240 4420

ECP3-95 240 4420

ECP3-150 372 6850

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

A WA EL[3 u] 1 ECLKZ SCLK LSR GSRN ECLK‘ ECLKZ SCLK READ DCNTL[5 u] DYNDELU u] DOSI PRMDET Cumml Muxes cm c507 LSR am as | m nos) yo. mun amp-n my...” mock usn mm mm" Black

2-31

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

Programmable I/O Cells (PIC)

Each PIC contains two PIOs connected to their respective sysI/O buffers as shown in Figure 2-32. The PIO Block

supplies the output data (DO) and the tri-state control signal (TO) to the sysI/O buffer and receives input from the

buffer. Table 2-11 provides the PIO signal list.

Figure 2-32. PIC Diagram

ONEGB

INA

IPA

DEL[3:0]

ECLK1, ECLK2

SCLK

LSR

ECLK1

ECLK2

SCLK

READ

DCNTL[5:0]

DYNDEL[7:0]

DQSI

PRMDET

GSRN

DDRLAT*

DDRCLKPOL*

ECLKDQSR*

DQCLK0*

DQCLK1*

DQSW*

CLK

CEOT

CEI

sysIO

Buffer

PADA

“T”

PADB

“C”

LSR

GSR

* Signals are available on left/right/top edges only.

** Signals are available on the left and right sides only

*** Selected PIO.

IOLD0

Tristate

Block

Output

Block

(ISI)

Input

Block

Control

Muxes

Read Control

Write Control

PIOB

PIOA

OPOSA

OPOSB

ONEGA**

ONEGB**

IPB

INCK

INDD

INB

IOLT0

I/Os in a DQS-12 Group, Except DQSN (Complement of DQS) I/Os

DQS Control Block

(One per DQS Group of 12 I/Os)***

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

same port as INCK. eption is the ONEGB port. used for tristate logic output block llip-llops. (POLK) for input and output/TS blocks. Connected lrom clock lSB. sources Entire PlO selects one of two sources usmg mux. DQS,STROBE. shifted strobe lor memory interfaces only transfer from DQS domain to SCLK domain. Used to guarantee lNDDFtX2 gearing by selectively enabling a D-Flip-Flop in dat- Dynamic input delay control bits. button PlO treated as clock PIO. path to distribute to primary clocks and PLL. ta Tristate signal from core (SDR) Control Two clocks edges, 90 degrees out of phase, used in output g ite Control Used for output and tristate logic at DQS only. Write Control Shilling ot write clocks lor specific DQS group. using 6 mately 25ps, 128 steps. Bit 7 is an invert (timing depe There is also a static control tor this 8-bit setting PIO Control Original delay code lrom DDFt DLl. Output Data Status tlag lrom DATAVALID logic. used to lDLOGIC and valid to core For Dosistrobe Read signal for DDR memory interta For Dosistrobe Unshitted DQS strobe lrom input pa PRMBDET For DQS,Strobe DQSI biased to go high whe core logic. GSRN Control lrom routing Global Set/Reset t. Slgnals available on lett/right/top edges only. 2. Selected PIO. PIO The PIO contains tour blocks: an input register bl block. These blocks contain registers for up tion logic. Input Register Block The input register blocks tor the be used to condition highrspeed

2-32

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as “T” and “C”) as shown in Figure 2-32.

The PAD Labels “T” and “C” distinguish the two PIOs. Approximately 50% of the PIO pairs on the left and right

edges of the device can be configured as true LVDS outputs. All I/O pairs can operate as LVDS inputs.

Table 2-11. PIO Signal List

PIO

The PIO contains four blocks: an input register block, output register block, tristate register block and a control logic

block. These blocks contain registers for operating in a variety of modes along with the necessary clock and selec-

tion logic.

Input Register Block

The input register blocks for the PIOs, in the left, right and top edges, contain delay elements and registers that can

be used to condition high-speed interface signals, such as DDR memory interfaces and source synchronous inter-

faces, before they are passed to the device core. Figure 2-33 shows the input register block for the left, right and

top edges. The input register block for the bottom edge contains one element to register the input signal and no

DDR registers. The following description applies to the input register block for PIOs in the left, right and top edges

only.

Name Type Description

INDD Input Data Register bypassed input. This is not the same port as INCK.

IPA, INA, IPB, INB Input Data Ports to core for input data

OPOSA, ONEGA1,

OPOSB, ONEGB1

Output Data Output signals from core. An exception is the ONEGB port, used for tristate logic

at the DQS pad.

CE PIO Control Clock enables for input and output block flip-flops.

SCLK PIO Control System Clock (PCLK) for input and output/TS blocks. Connected from clock ISB.

LSR PIO Control Local Set/Reset

ECLK1, ECLK2 PIO Control Edge clock sources. Entire PIO selects one of two sources using mux.

ECLKDQSR1Read Control From DQS_STROBE, shifted strobe for memory interfaces only.

DDRCLKPOL1Read Control Ensures transfer from DQS domain to SCLK domain.

DDRLAT1Read Control Used to guarantee INDDRX2 gearing by selectively enabling a D-Flip-Flop in dat-

apath.

DEL[3:0] Read Control Dynamic input delay control bits.

INCK To Clock Distribution

and PLL

PIO treated as clock PIO, path to distribute to primary clocks and PLL.

TS Tristate Data Tristate signal from core (SDR)

DQCLK01, DQCLK11Write Control Two clocks edges, 90 degrees out of phase, used in output gearing.

DQSW2Write Control Used for output and tristate logic at DQS only.

DYNDEL[7:0] Write Control Shifting of write clocks for specific DQS group, using 6:0 each step is approxi-

mately 25ps, 128 steps. Bit 7 is an invert (timing depends on input frequency).

There is also a static control for this 8-bit setting, enabled with a memory cell.

DCNTL[6:0] PIO Control Original delay code from DDR DLL

DATAVALID1Output Data Status flag from DATAVALID logic, used to indicate when input data is captured in

IOLOGIC and valid to core.

READ For DQS_Strobe Read signal for DDR memory interface

DQSI For DQS_Strobe Unshifted DQS strobe from input pad

PRMBDET For DQS_Strobe DQSI biased to go high when DQSI is tristate, goes to input logic block as well as

core logic.

GSRN Control from routing Global Set/Reset

1. Signals available on left/right/top edges only.

2. Selected PIO.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

5 registered with the system d negative edges of the modified DOS ng DDR Generic mode, creating two data ronized to the system clock to generate two ut registers on the left and right sides. The gearbox func- onverts it as four data streams, INA, IPA, INB and IPB. ters are synchronized to the edge clock and then to the system lurther information on the use of the gearbox function. of the clock used in the synchronization registers. It ensures ader e system clock domain from the ECLKDQSR (DDR Memory lnter1ace DDRLAT signal is used to ensure the data transfer from the syn d gearbox registers. DDFlLAT signals are generated in the DOS Read Control Logic DQS read control logic. ing the DOS strobe in this module is discussed in the DDR Memory 5 , LarliceECPS High-Sgeed IZO interface for more information on

2-33

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

Input signals are fed from the sysI/O buffer to the input register block (as signal DI). If desired, the input signal can

bypass the register and delay elements and be used directly as a combinatorial signal (INDD), a clock (INCK) and,

in selected blocks, the input to the DQS delay block. If an input delay is desired, designers can select either a fixed

delay or a dynamic delay DEL[3:0]. The delay, if selected, reduces input register hold time requirements when

using a global clock.

The input block allows three modes of operation. In single data rate (SDR) the data is registered with the system

clock by one of the registers in the single data rate sync register block.

In DDR mode, two registers are used to sample the data on the positive and negative edges of the modified DQS

(ECLKDQSR) in the DDR Memory mode or ECLK signal when using DDR Generic mode, creating two data

streams. Before entering the core, these two data streams are synchronized to the system clock to generate two

data streams.

A gearbox function can be implemented in each of the input registers on the left and right sides. The gearbox func-

tion takes a double data rate signal applied to PIOA and converts it as four data streams, INA, IPA, INB and IPB.

The two data streams from the first set of DDR registers are synchronized to the edge clock and then to the system

clock before entering the core. Figure 2-30 provides further information on the use of the gearbox function.

The signal DDRCLKPOL controls the polarity of the clock used in the synchronization registers. It ensures ade-

quate timing when data is transferred to the system clock domain from the ECLKDQSR (DDR Memory Interface

mode) or ECLK (DDR Generic mode). The DDRLAT signal is used to ensure the data transfer from the synchroni-

zation registers to the clock transfer and gearbox registers.

The ECLKDQSR, DDRCLKPOL and DDRLAT signals are generated in the DQS Read Control Logic Block. See

Figure 2-37 for an overview of the DQS read control logic.

Further discussion about using the DQS strobe in this module is discussed in the DDR Memory section of this data

sheet.

Please see TN1180, LatticeECP3 High-Speed I/O Interface for more information on this topic.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

rn it?“ ll L 9 l r rn CE/SET/REST details Output Register Block ck registers signals from the core of the device before they are pass it and right PlOs contain registers for SDR and full DDFt operation ft and right sides except it does not support ODDFlXZ gearing 01 out memory interfacesThe PIO blocks on the bottom contain the SDFl reg ut gearing. re 2734 shows the Output Register Block for PlOs on the left and righ SDFl mode, OPOSA leeds one 01 the fliprllops that then feeds th pe or latch. In DDR mode, two of the inputs are fed into regi clock cycle, one 01 the registered outputs is also latched. A multiplexer running olf the same clock is used to switch th the output. A gearbox function can be implemented in the output OPOSB and ONEGB. All tour data inputs are re are also latched. The data is then output at a hig clocks. DQCLKO and DQCLKt are used domain. These signals are generated in the DOS write control logic. Please see TN1180, Lat‘liceECPS HighrSpeed l/O Interface

2-34

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

Figure 2-33. ECP3-70/95 (E or EA) Input Register Block for Left, Right and Top Edges

Output Register Block

The output register block registers signals from the core of the device before they are passed to the sysI/O buffers.

The blocks on the left and right PIOs contain registers for SDR and full DDR operation. The topside PIO block is the

same as the left and right sides except it does not support ODDRX2 gearing of output logic. ODDRX2 gearing is

used in DDR3 memory interfaces.The PIO blocks on the bottom contain the SDR registers and generic DDR inter-

face without gearing.

Figure 2-34 shows the Output Register Block for PIOs on the left and right edges.

In SDR mode, OPOSA feeds one of the flip-flops that then feeds the output. The flip-flop can be configured as a

Dtype or latch. In DDR mode, two of the inputs are fed into registers on the positive edge of the clock. At the next

clock cycle, one of the registered outputs is also latched.

A multiplexer running off the same clock is used to switch the mux between the 11 and 01 inputs that will then feed

the output.

A gearbox function can be implemented in the output register block that takes four data streams: OPOSA, ONEGA,

OPOSB and ONEGB. All four data inputs are registered on the positive edge of the system clock and two of them

are also latched. The data is then output at a high rate using a multiplexer that runs off the DQCLK0 and DQCLK1

clocks. DQCLK0 and DQCLK1 are used in this case to transfer data from the system clock to the edge clock

domain. These signals are generated in the DQS Write Control Logic block. See Figure 2-37 for an overview of the

DQS write control logic.

Please see TN1180, LatticeECP3 High-Speed I/O Interface for more information on this topic.

Further discussion on using the DQS strobe in this module is discussed in the DDR Memory section of this data

sheet.

(From sysIO

Buffer)

D Q

DDRCLKPOL

Dynamic Delay

Fixed Delay

D Q

SCLK

D Q

INA

INB

IPB

IPA

D Q

DDRLAT

Config bit

INCLK**

DEL[3:0]

INDD

D Q

DDR Registers

CLKP

ECLK2

Synch Registers

ECLKDQSR

ECLK1

ECLK2

Clock Transfer &

Gearing Registers*

* Only on the left and right sides.

** Selected PIO.

Note: Simplified diagram does not show CE/SET/REST details.

To DQSI**

1 0

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

l l l ‘ u k DDR Gearing &‘ i'r ster ‘ ISICurreclion ‘ neg sters i Conlig Bit istate Register Block tristate register block registers trirstate control signals lrom the core of l/O butters. The block contains a register lor SDR operation and SDR and nonvgearing DDFl modes, TS input leeds one ol t mode, the registerTS input is led into another register that is clo output ol this register is used as a tristate control. ISI Calibration The setting for InterrSymbol Interference (ISI) cancell available in the DDFlXZ modes. ISI calibration se 12 group may have a dilferent ISI calibration sett The ISI block extends output signals at cer consists 01 a long strings of 0‘s to lon quick, successive transitions lrom 010 cause these symbols to interfer block will stretch out the binary 0 Output Logic DO

2-35

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

Figure 2-34. ECP3-70/95 (E or EA) Output and Tristate Block for Left and Right Edges

Tristate Register Block

The tristate register block registers tri-state control signals from the core of the device before they are passed to the

sysI/O buffers. The block contains a register for SDR operation and an additional register for DDR operation.

In SDR and non-gearing DDR modes, TS input feeds one of the flip-flops that then feeds the output. In DDRX2

mode, the register TS input is fed into another register that is clocked using the DQCLK0 and DQCLK1 signals. The

output of this register is used as a tristate control.

ISI Calibration

The setting for Inter-Symbol Interference (ISI) cancellation occurs in the output register block. ISI correction is only

available in the DDRX2 modes. ISI calibration settings exist once per output register block, so each I/O in a DQS-

12 group may have a different ISI calibration setting.

The ISI block extends output signals at certain times, as a function of recent signal history. So, if the output pattern

consists of a long strings of 0's to long strings of 1's, there are no delays on output signals. However, if there are

quick, successive transitions from 010, the block will stretch out the binary 1. This is because the long trail of 0's will

cause these symbols to interfere with the logic 1. Likewise, if there are quick, successive transitions from 101, the

block will stretch out the binary 0. This block is controlled by a 3-bit delay control that can be set in the DQS control

logic block.

For more information about this topic, please see the list of technical documentation at the end of this data sheet.

D Q

ONEGB

OPOSA

OPOSB

ONEGA

D Q

SCLK

DQCLK1

Config Bit

DQCLK0

ISI

D Q

Tristate Logic

Output Logic

Clock

Transfer

Registers

DDR Gearing &

ISI Correction

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

rce synchronous and DDR1, detailed below. pporting DDR1, DDR2, and DDR3 memory ith the DOS control logic block. Figure 2-35 upport the dedicated DOS and D084: pins with t DDR memory and Generic DDR interfaces. ments on the left and right sides but do not support gearing on the on output/tristate DDR3 memory are removed on the top side. ual function in the Logic Signal Connections table in this data shee Descriptions table. The DQS signal from the bus is used to stro register blocks. interfaces on the left, right and top edges are desig 1 data. ng on the Left, Right and Top Edges I: I: DOS

2-36

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

Control Logic Block

The control logic block allows the selection and modification of control signals for use in the PIO block.

DDR Memory Support

Certain PICs have additional circuitry to allow the implementation of high-speed source synchronous and DDR1,

DDR2 and DDR3 memory interfaces. The support varies by the edge of the device as detailed below.

Left and Right Edges

The left and right sides of the PIC have fully functional elements supporting DDR1, DDR2, and DDR3 memory

interfaces. One of every 12 PIOs supports the dedicated DQS pins with the DQS control logic block. Figure 2-35

shows the DQS bus spanning 11 I/O pins. Two of every 12 PIOs support the dedicated DQS and DQS# pins with

the DQS control logic block.

Bottom Edge

PICs on the bottom edge of the device do not support DDR memory and Generic DDR interfaces.

Top Edge

PICs on the top side are similar to the PIO elements on the left and right sides but do not support gearing on the

output registers. Hence, the modes to support output/tristate DDR3 memory are removed on the top side.

The exact DQS pins are shown in a dual function in the Logic Signal Connections table in this data sheet. Addi-

tional detail is provided in the Signal Descriptions table. The DQS signal from the bus is used to strobe the DDR

data from the memory into input register blocks. Interfaces on the left, right and top edges are designed for DDR

memories that support 10 bits of data.

Figure 2-35. DQS Grouping on the Left, Right and Top Edges

DLL Calibrated DQS Delay Block

Source synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at

the input register. For most interfaces, a PLL is used for this adjustment. However, in DDR memories the clock

PIO B

PIO A

PIO B

PIO A

Assigned

DQS Pin

DQS Delay

sysIO

Buffer PADA "T"

PADB "C"

LVDS Pair

PADA "T"

PADB "C"

LVDS Pair

PIO A

PIO B

PADA "T"

PADB "C"

LVDS Pair

PIO A

PIO B

PADA "T"

PADB "C"

LVDS Pair

PIO A

PIO B

PADA "T"

PADB "C"

LVDS Pair

PIO A

PIO B

PADA "T"

PADB "C"

LVDS Pair

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

LL on the right will generate temperature, voltage and pro LL communicates the required delay to lrom the PAD through a DOS control logic ck consists ol DOS Read Control logic block Control logic that generates the control signals agram is shown in Figure 2737, which shows how the erated by the DDR DLL on its side and delays the incoming R is routed to 10 or 11 DO pads covered by that DOS signal. that generates a DDRCLKPOL signal, which controls the polarity of ter blocks. The DQS Read control logic also generates a DDRLAT ransfer data from the lirst set 01 DDR register to the second set 01 mode lor DDR3 memory interface. erates the DQCLKO and DQCLKt clocks used to control the ou generates the DDR data output and the DOS output. They are also output through the DOS output register block. In addition to the S Write control block also uses a Dynamic Delay DYN DEL [7:0] attrip o accomplish the write leveling found in DDR3 memory. Write lev er implementation. The DYN DELAY can set 128 possible delay step I invert the clock for a 180-degree shilt of the incoming clock. enerate the DOS output in the DOS output register block. 6 and Figure 2737 show how the DOS transition signals that are rout ee TN1180, LatticeECPS HighrSpeed l/O Interface for more inlor

2-37

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

(referred to as DQS) is not free-running so this approach cannot be used. The DQS Delay block provides the

required clock alignment for DDR memory interfaces.

The delay required for the DQS signal is generated by two dedicated DLLs (DDR DLL) on opposite side of the

device. Each DLL creates DQS delays in its half of the device as shown in Figure 2-36. The DDR DLL on the left

side will generate delays for all the DQS Strobe pins on Banks 0, 7 and 6 and DDR DLL on the right will generate

delays for all the DQS pins on Banks 1, 2 and 3. The DDR DLL loop compensates for temperature, voltage and pro-

cess variations by using the system clock and DLL feedback loop. DDR DLL communicates the required delay to

the DQS delay block using a 7-bit calibration bus (DCNTL[6:0])

The DQS signal (selected PIOs only, as shown in Figure 2-35) feeds from the PAD through a DQS control logic

block to a dedicated DQS routing resource. The DQS control logic block consists of DQS Read Control logic block

that generates control signals for the read side and DQS Write Control logic that generates the control signals

required for the write side. A more detailed DQS control diagram is shown in Figure 2-37, which shows how the

DQS control blocks interact with the data paths.

The DQS Read control logic receives the delay generated by the DDR DLL on its side and delays the incoming

DQS signal by 90 degrees. This delayed ECLKDQSR is routed to 10 or 11 DQ pads covered by that DQS signal.

This block also contains a polarity control logic that generates a DDRCLKPOL signal, which controls the polarity of

the clock to the sync registers in the input register blocks. The DQS Read control logic also generates a DDRLAT

signal that is in the input register block to transfer data from the first set of DDR register to the second set of DDR

registers when using the DDRX2 gearbox mode for DDR3 memory interface.

The DQS Write control logic block generates the DQCLK0 and DQCLK1 clocks used to control the output gearing

in the Output register block which generates the DDR data output and the DQS output. They are also used to con-

trol the generation of the DQS output through the DQS output register block. In addition to the DCNTL [6:0] input

from the DDR DLL, the DQS Write control block also uses a Dynamic Delay DYN DEL [7:0] attribute which is used

to further delay the DQS to accomplish the write leveling found in DDR3 memory. Write leveling is controlled by the

DDR memory controller implementation. The DYN DELAY can set 128 possible delay step settings. In addition, the

most significant bit will invert the clock for a 180-degree shift of the incoming clock. This will generate the DQSW

signal used to generate the DQS output in the DQS output register block.

Figure 2-36 and Figure 2-37 show how the DQS transition signals that are routed to the PIOs.

Please see TN1180, LatticeECP3 High-Speed I/O Interface for more information on this topic.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

sou WWW HUT” DDR DLL (nugm SERDES nd Transmon Dem: Logm DD "9 shared ccnlvgurahon I/Os and decimated conﬁguramn v05, sou sou \ \ sum som‘ \som som‘ axuea 2 W99 { DOS De‘ay Cumrm Bus ECLKI ECLKZ DOCLKO Doch DDRLAT DDRCLKPOL ECLKDQSR DATAVALID

2-38

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

Figure 2-36. Edge Clock, DLL Calibration and DQS Local Bus Distribution

DQS DQS DQS DQS DQS DQS DQS DQS DQS

DQSDQSDQSDQS DQS DQS DQS

DQS DQS DQS DQS DQS DQS DQS

Bank 0 Bank 1 Configuration Bank

Bank 2

Bank 7Bank 6

Bank 3

DQS Strobe and Transition Detect Logic

I/O Ring

*Includes shared configuration I/Os and dedicated configuration I/Os.

SERDES

DDR DLL

(Left)

DDR DLL

(Right)

DQS Delay Control Bus

ECLK1

ECLK2

DQCLK0

DQCLK1

DDRLAT

DDRCLKPOL

ECLKDQSR

DATAVALID

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

4 O DDR Data Pad er Block as Output Register Block DQS DOS Write Control Logic DOS Read Controi Logic DQS Deiay Biock DDR DLL Polarity Control Logic In a typicai DDR Memory interface design, the phase reiati the internal system clock (during the READ cycle) is unkno to transfer data between these domains. A clock pola the domain transfer between DOS (delayed) and the s istered in the synchronizing registers in the input cycle lor the correct ciock polarity. Prior to the READ operation in DDR memo drives DQS low at the start of the prea ambie state. This signal is used to co DDR3 Memory Support

2-39

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

Figure 2-37. DQS Local Bus

Polarity Control Logic

In a typical DDR Memory interface design, the phase relationship between the incoming delayed DQS strobe and

the internal system clock (during the READ cycle) is unknown. The LatticeECP3 family contains dedicated circuits

to transfer data between these domains. A clock polarity selector is used to prevent set-up and hold violations at

the domain transfer between DQS (delayed) and the system clock. This changes the edge on which the data is reg-

istered in the synchronizing registers in the input register block. This requires evaluation at the start of each READ

cycle for the correct clock polarity.

Prior to the READ operation in DDR memories, DQS is in tristate (pulled by termination). The DDR memory device

drives DQS low at the start of the preamble state. A dedicated circuit detects the first DQS rising edge after the pre-

amble state. This signal is used to control the polarity of the clock to the synchronizing registers.

DDR3 Memory Support

LatticeECP3 supports the read and write leveling required for DDR3 memory interfaces.

Read leveling is supported by the use of the DDRCLKPOL and the DDRLAT signals generated in the DQS Read

Control logic block. These signals dynamically control the capture of the data with respect to the DQS at the input

DDR DLL

DQS Write Control Logic

DQS Read Control Logic

Data Output Register Block

DQCLK0

DQCLK1

DQSW

DDRLAT

DDRCLKPOL

ECLKDQSR

DCNTL[6:0]

Data Input Register Block

DQS

Pad

DDR Data

Pad

DQS Output Register Block

DQS Delay Block

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

y inter1ace. In addition, it supports maiion, reler to the syle section 01 this Lat‘liceECPS HighrSpeed l/O Interface nformatton on DDR Memory interface impler a sysl/O buffer. These bulfers are arranged around the s. The sysl/O buffers allow users to implement the Wlde variety ng LVDS, BLVDS, HSTL, SSTL Class | & II, LVCMOS, LV'ITL, buffer banks: SlX banks for user l/Os arranged two per side. The bank nks on the lower right and left sides. The seventh sysl/O buﬂer b to Bank 2 and has dedicated/shared l/Os for conﬁguration. When a 5 available as a user l/O. Each bank is capable of supporting multi own l/O supply voltage (Vcclo)- In addition, each bank, except the C an and VREF2v which allow it to be completely independent from the c shares VREF‘ and VREF2 from sysl/O bank 1 and right Side shares 2738 shows the seven banks and their associated supplies. P3 dewces, singlerended output butters and ratioed input buffers (LV‘ITL mo. LV'I'I’L, chmosea, chmoszs and LVCMOS12 can also b fVCCIO- bank can support up to two separate VREF voltages, VREF‘ and VR d input buffers. Some dedicated l/O pins in a bank can be cc ch l/O Is individually conﬁgurable based on the bank's supply a

2-40

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

To accomplish write leveling in DDR3, each DQS group has a slightly different delay that is set by DYN DELAY[7:0]

in the DQS Write Control logic block. The DYN DELAY can set 128 possible delay step settings. In addition, the

most significant bit will invert the clock for a 180-degree shift of the incoming clock.

LatticeECP3 input and output registers can also support DDR gearing that is used to receive and transmit the high

speed DDR data from and to the DDR3 Memory.

LatticeECP3 supports the 1.5V SSTL I/O standard required for the DDR3 memory interface. In addition, it supports

on-chip termination to VTT on the DDR3 memory input pins. For more information, refer to the sysIO section of this

data sheet.

Please see TN1180, LatticeECP3 High-Speed I/O Interface for more information on DDR Memory interface imple-

mentation in LatticeECP3.

sysI/O Buffer

Each I/O is associated with a flexible buffer referred to as a sysI/O buffer. These buffers are arranged around the

periphery of the device in groups referred to as banks. The sysI/O buffers allow users to implement the wide variety

of standards that are found in today’s systems including LVDS, BLVDS, HSTL, SSTL Class I & II, LVCMOS, LVTTL,

LVPECL, PCI.

sysI/O Buffer Banks

LatticeECP3 devices have six sysI/O buffer banks: six banks for user I/Os arranged two per side. The banks on the

bottom side are wraparounds of the banks on the lower right and left sides. The seventh sysI/O buffer bank (Config-

uration Bank) is located adjacent to Bank 2 and has dedicated/shared I/Os for configuration. When a shared pin is

not used for configuration it is available as a user I/O. Each bank is capable of supporting multiple I/O standards.

Each sysI/O bank has its own I/O supply voltage (VCCIO). In addition, each bank, except the Configuration Bank,

has voltage references, VREF1 and VREF2, which allow it to be completely independent from the others. The Config-

uration Bank top side shares VREF1 and VREF2 from sysI/O bank 1 and right side shares VREF1 and VREF2 from

sysI/O bank 2. Figure 2-38 shows the seven banks and their associated supplies.

In LatticeECP3 devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS and PCI) are pow-

ered using VCCIO. LVTTL, LVCMOS33, LVCMOS25 and LVCMOS12 can also be set as fixed threshold inputs inde-

pendent of VCCIO.

Each bank can support up to two separate VREF voltages, VREF1 and VREF2, that set the threshold for the refer-

enced input buffers. Some dedicated I/O pins in a bank can be configured to be a reference voltage supply pin.

Each I/O is individually configurable based on the bank’s supply and reference voltages.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

SERDES Quads BOTTOM iceECP3 devices coniain two iypes of sysl/O buﬂer pairs. Top (Bank 0 and Bank 1) and Bottom sysllO Bulfer The sysI/O buffer pairs in me iop banks of the device co single-ended inpui buffers (boih ratioed and refere ﬁgured as a diﬂeremial input. Only the iop edge b The two pads in me pair are described as “1r side of ihe diﬂereniial input buffer and me differential input buffer. On ihe top and bonom sides, iher ior DO and DOS pins for DD IIO, PCI, TR»LVDS (iransiiio o g 5'“? *2 § VREFuz) VREF212) Vccwoz GND VRE VR .I.H 9IH

2-41

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

Figure 2-38. LatticeECP3 Banks

LatticeECP3 devices contain two types of sysI/O buffer pairs.

1. Top (Bank 0 and Bank 1) and Bottom sysI/O Buffer Pairs (Single-Ended Outputs Only)

The sysI/O buffer pairs in the top banks of the device consist of two single-ended output drivers and two sets of

single-ended input buffers (both ratioed and referenced). One of the referenced input buffers can also be con-

figured as a differential input. Only the top edge buffers have a programmable PCI clamp.



The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive

side of the differential input buffer and the comp (complementary) pad is associated with the negative side of

the differential input buffer. 



On the top and bottom sides, there is no support for programmable on-chip input termination, which is required

for DQ and DQS pins for DDR3 interface. This side is ideal for ADDR/CMD signals of DDR3, general purpose 

I/O, PCI, TR-LVDS (transition reduced LVDS) or LVDS inputs. Only the top I/O banks support hot socketing

with IDK specified under the Hot Socketing Specifications. The configuration bank is not hot-socketable.

REF1(0)

GND

CCIO0

VREF2(0)

VREF1(1)

GND

CCIO1

REF2(1)

VREF1(7)

GND

VCCIO7

VREF2(7)

VREF1(2)

GND

VCCIO2

VREF2(2)

VREF1(3)

GND

VCCIO3

VREF2(3)

RIGHT

Bank 2

Configuration

Bank

Bank 3

Bank 7

Bank 6

VREF1(6)

GND

VCCIO6

VREF2(6)

Bank 0 Bank 1

BOTTOM

JTAG Bank

SERDES

Quads

LEFT

TOP

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

ks the two pads in the pair oSitive side of the differential l/O, e differential l/O. tial, static or dynamic) is supported on 5 no support for hotrsockeiing on these vers are available on 50% of the buffer pairs on the ed Outputs, Only on Shared Pins When Not Used by sist of single-ended output drivers and single-ended input bufr renced input buﬂer can also be configured as a differential input. d as “true" and “comp“, where the true pad is associated with the po and the comp (complementary) pad is associated with the negative 5 ly available on top banks (PCI clamps are used primarily on inputs the receiving end) can also be used on inputs. Typical sysl/O IIO Behavior During Power-up reset (FOR) signal is deactivated when Vcci Vccloa and Vcc h Fl signal is deactivated, the FPGA core logic becomes active. l t all other VCCIO banks are active with valid input logic levels to properly co ks that are critical to the application. For more information about logic levels during powerrup in LatticeECPa devices, see the list of is data sheet. he Vcc and VccAux supply the power to the FPGA core fabric, wh rs. In order to simplify system design while providing conSistent that the l/O buﬂers be powered-up prior to the FPGA core fabri together With the Vcc and VCCAUX supplies. Supported sysl/O Standards The LaiticeECP3 sysl/O buﬂer supports both singlere be further subdivided into LVCMOS, LVTTL and 1.5V, 1.8V, 2.5V and 3.3V standards. In the LV options for drive strength, slew rates, bus m open drain. Other singlerended standards include LVDS, BLVDS, LVPECL, MLV Fleduced LVDS), differential SSTL an With their supply and reference v sysl/O buffer to support a variet LatticeECPa syle Usage Guide

2-42

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

2. Left and Right (Banks 2, 3, 6 and 7) sysI/O Buffer Pairs (50% Differential and 100% Single-Ended Out-

puts)

The sysI/O buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two

sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. One of the

referenced input buffers can also be configured as a differential input. In these banks the two pads in the pair

are described as “true” and “comp”, where the true pad is associated with the positive side of the differential I/O,

and the comp (complementary) pad is associated with the negative side of the differential I/O. 



In addition, programmable on-chip input termination (parallel or differential, static or dynamic) is supported on

these sides, which is required for DDR3 interface. However, there is no support for hot-socketing on these

sides as the clamp is always present.



LVDS, RSDS, PPLVDS and Mini-LVDS differential output drivers are available on 50% of the buffer pairs on the

left and right banks.

3. Configuration Bank sysI/O Buffer Pairs (Single-Ended Outputs, Only on Shared Pins When Not Used by

Configuration)

The sysI/O buffers in the Configuration Bank consist of single-ended output drivers and single-ended input buf-

fers (both ratioed and referenced). The referenced input buffer can also be configured as a differential input. 



The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive

side of the differential input buffer and the comp (complementary) pad is associated with the negative side of

the differential input buffer.

Programmable PCI clamps are only available on top banks (PCI clamps are used primarily on inputs and bidirec-

tional pads to reduce ringing on the receiving end) can also be used on inputs.

Typical sysI/O I/O Behavior During Power-up

The internal power-on-reset (POR) signal is deactivated when VCC, VCCIO8 and VCCAUX have reached satisfactory

levels. After the POR signal is deactivated, the FPGA core logic becomes active. It is the user’s responsibility to

ensure that all other VCCIO banks are active with valid input logic levels to properly control the output logic states of

all the I/O banks that are critical to the application. For more information about controlling the output logic state with

valid input logic levels during power-up in LatticeECP3 devices, see the list of technical documentation at the end

of this data sheet.

The VCC and VCCAUX supply the power to the FPGA core fabric, whereas the VCCIO supplies power to the I/O buf-

fers. In order to simplify system design while providing consistent and predictable I/O behavior, it is recommended

that the I/O buffers be powered-up prior to the FPGA core fabric. VCCIO supplies should be powered-up before or

together with the VCC and VCCAUX supplies.

Supported sysI/O Standards

The LatticeECP3 sysI/O buffer supports both single-ended and differential standards. Single-ended standards can

be further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVCMOS 1.2V,

1.5V, 1.8V, 2.5V and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individual configuration

options for drive strength, slew rates, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and

open drain. Other single-ended standards supported include SSTL and HSTL. Differential standards supported

include LVDS, BLVDS, LVPECL, MLVDS, RSDS, Mini-LVDS, PPLVDS (point-to-point LVDS), TRLVDS (Transition

Reduced LVDS), differential SSTL and differential HSTL. Tables 2-13 and 2-14 show the I/O standards (together

with their supply and reference voltages) supported by LatticeECP3 devices. For further information on utilizing the

sysI/O buffer to support a variety of standards please see TN1177, LatticeECP3 sysIO Usage Guide.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

Term e‘y e E ma ion 1 8 _g_. Programmablevesws|ance140. so and so Ohms) Inpul s for inpuk modes. xio put com 3 memory controller imp‘er m er implemenlanon. "P 20 j> Za Oﬂrcmp Oowp 4— E —> 'vu mus| be \en unsung «w (m: \evmmauan Diﬂerenlial Input on Optians for Input Modes ,TVPE TERMINATE to V17“: DIFFHENTIAL TERMINATION RES LVDSZS p 80. 100. 120 BLVDSZS b 80, 100, 120 MLVDS p 80,100.120 HSTL187| 40‘ 50, 60 p HSTL187|| 40, 50, 60 p HSTL18D7| 40, 50, 6O HSTL18D7|| 40‘ 50, 6O HSTL157| 40‘ 50, 60 HSTL15D7| 40, 50, 60 SSTL257| 40, 50, 60 SSTLZSJI 40, 50‘ 60 SSTLZSDJ 40‘ 50, 6O SSTL25D7|| 40, 50, 6O SSTL187| 40, 50, SSTL187|| 4 SSTL18D7| 4 SSTL18D7|| SSTL15 SSTL15D 1. TERMINATE to

2-43

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

On-Chip Programmable Termination

The LatticeECP3 supports a variety of programmable on-chip terminations options, including:

• Dynamically switchable Single Ended Termination for SSTL15 inputs with programmable resistor values of 40,

50, or 60 ohms. This is particularly useful for low power JEDEC compliant DDR3 memory controller imple-

mentations. External termination to Vtt should be used for DDR2 memory controller implementation.

• Common mode termination of 80, 100, 120 ohms for differential inputs

Figure 2-39. On-Chip Termination

See Table 2-12 for termination options for input modes.

Table 2-12. On-Chip Termination Options for Input Modes

IO_TYPE TERMINATE to VTT1, 2 DIFFRENTIAL TERMINATION RESISTOR1

LVDS25 þ 80, 100, 120

BLVDS25 þ 80, 100, 120

MLVDS þ 80, 100, 120

HSTL18_I 40, 50, 60 þ

HSTL18_II 40, 50, 60 þ

HSTL18D_I 40, 50, 60 þ

HSTL18D_II 40, 50, 60 þ

HSTL15_I 40, 50, 60 þ

HSTL15D_I 40, 50, 60 þ

SSTL25_I 40, 50, 60 þ

SSTL25_II 40, 50, 60 þ

SSTL25D_I 40, 50, 60 þ

SSTL25D_II 40, 50, 60 þ

SSTL18_I 40, 50, 60 þ

SSTL18_II 40, 50, 60 þ

SSTL18D_I 40, 50, 60 þ

SSTL18D_II 40, 50, 60 þ

SSTL15 40, 50, 60 þ

SSTL15D 40, 50, 60 þ

1. TERMINATE to VTT and DIFFRENTIAL TERMINATION RESISTOR when turn on can only have

one setting per bank. Only left and right banks have this feature.

Use of TERMINATE to VTT and DIFFRENTIAL TERMINATION RESISTOR are mutually exclusive

in an I/O bank.

On-chip termination tolerance +/- 20%

2. External termination to VTT should be used when implementing DDR2 memory controller.

Parallel Single-Ended Input Differential Input

Vtt

Control Signal

Off-chip On-Chip

Programmable resistance (40, 50 and 60 Ohms)

Off-chip On-Chip

Vtt*

*Vtt must be left floating for this termination

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

, LatticeECPS syle Usage Guide mpensate lor the difficulty of the most useful for the Input n filter acts as a tunable lilter with re are four settings available: 0 (none), l/O bulfers, the two bits of setting is set have a unique equalization setting Within a nsure predictable behavtor during powerrup and power- l/Os remain in trirstate until the power supply voltage is on, leakage into l/O pins is controlled within specified limits. e DC and Switching Characteristics in this data sheet. ding Sublayer) els of embedded SERDES/PCS arranged in quads at the botto rate. Figure 2740 shows the position 01 the quad blocks for the Lattic ation of available SERDES Quads for all devices. upports a range of popular serial protocols, including: GbE . 1000 Base CS/SX/LX and SGMII) DI (3G, HD, so) SONET/SDH (STSVS, STSV12, STSV4B) quad contains four dedicated SERDES for high speed, full dup 8 block that interfaces to the SERDES channels and contains rds listed above. The PCS block also contains intertace logict tocol support can also be bypassed to allow raw 8-bit or 10 Even though the SERDES/PCS blocks are arranged in dua With the use 01 dedicated, per channel +1, +2 and +1 together to term larger data pipes. For information on how to use the SERDES/PC multiple protocols and baud rates within LatticeECPS SERDES/PCS Usage Guide.

2-44

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

Please see TN1177, LatticeECP3 sysIO Usage Guide for on-chip termination usage and value ranges.

Equalization Filter

Equalization filtering is available for single-ended inputs on both true and complementary I/Os, and for differential

inputs on the true I/Os on the left, right, and top sides. Equalization is required to compensate for the difficulty of

sampling alternating logic transitions with a relatively slow slew rate. It is considered the most useful for the Input

DDRX2 modes, used in DDR3 memory, LVDS, or TRLVDS signaling. Equalization filter acts as a tunable filter with

settings to determine the level of correction. In the LatticeECP3 devices, there are four settings available: 0 (none),

1, 2 and 3. The default setting is 0. The equalization logic resides in the sysI/O buffers, the two bits of setting is set

uniquely in each input IOLOGIC block. Therefore, each sysI/O can have a unique equalization setting within a

DQS-12 group.

Hot Socketing

LatticeECP3 devices have been carefully designed to ensure predictable behavior during power-up and power-

down. During power-up and power-down sequences, the I/Os remain in tri-state until the power supply voltage is

high enough to ensure reliable operation. In addition, leakage into I/O pins is controlled within specified limits.

Please refer to the Hot Socketing Specifications in the DC and Switching Characteristics in this data sheet.

SERDES and PCS (Physical Coding Sublayer)

LatticeECP3 devices feature up to 16 channels of embedded SERDES/PCS arranged in quads at the bottom of the

devices supporting up to 3.2Gbps data rate. Figure 2-40 shows the position of the quad blocks for the LatticeECP3-

150 devices. Table 2-14 shows the location of available SERDES Quads for all devices.

The LatticeECP3 SERDES/PCS supports a range of popular serial protocols, including:

• PCI Express 1.1

• Ethernet (XAUI, GbE - 1000 Base CS/SX/LX and SGMII)

• Serial RapidIO

• SMPTE SDI (3G, HD, SD)

• CPRI

• SONET/SDH (STS-3, STS-12, STS-48)

Each quad contains four dedicated SERDES for high speed, full duplex serial data transfer. Each quad also has a

PCS block that interfaces to the SERDES channels and contains protocol specific digital logic to support the stan-

dards listed above. The PCS block also contains interface logic to the FPGA fabric. All PCS logic for dedicated pro-

tocol support can also be bypassed to allow raw 8-bit or 10-bit interfaces to the FPGA fabric.

Even though the SERDES/PCS blocks are arranged in quads, multiple baud rates can be supported within a quad

with the use of dedicated, per channel 1, 2 and 11 rate dividers. Additionally, multiple quads can be arranged

together to form larger data pipes.

For information on how to use the SERDES/PCS blocks to support specific protocols, as well on how to combine

multiple protocols and baud rates within a device, please refer to TN1176, LatticeECP3 SERDES/PCS Usage

Guide.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

5 $2 5 5 E 5 3’ ESIPCS smuzms sERDEs/Pcs SERDEs/Pcs ; mm D man a om A am :2 u EHDES Standard Suppon Dala Hale Number of (Mbps) General/Link Width 2500 x1, X2, x4 1250, 2500 x1 1250 x1 3125 x4 al Rapid‘O Type I, 1250. x1, x4 al Rapile Type H, 2500. ial Rapidxo Type III 3125 CPRl-1, 614.4, CPRl-2, 1228.8, CPRl-S, 2457.6, CPRl-4 3072.0 143‘, 1 SD-SDI 12772 (259M, 344M) 360' 54 HD-SDI 148 (292M) SG-SDI (424M) SONET—STS-ﬁ2 Lamce ECP3 SERDES/PCS Usage Gulde

2-45

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

Figure 2-40. SERDES/PCS Quads (LatticeECP3-150)

Table 2-13. LatticeECP3 SERDES Standard Support

Standard

Data Rate

(Mbps)

Number of

General/Link Width Encoding Style

PCI Express 1.1 2500 x1, x2, x4 8b10b

Gigabit Ethernet 1250, 2500 x1 8b10b

SGMII 1250 x1 8b10b

XAUI 3125 x4 8b10b

Serial RapidIO Type I,

Serial RapidIO Type II,

Serial RapidIO Type III

1250,

2500,

3125

x1, x4 8b10b

CPRI-1,

CPRI-2,

CPRI-3,

CPRI-4

614.4,

1228.8,

2457.6,

3072.0

x1 8b10b

SD-SDI

(259M, 344M)

1431,

1771,

270,

360,

540

x1 NRZI/Scrambled

HD-SDI

(292M)

1483.5,

1485 x1 NRZI/Scrambled

3G-SDI

(424M)

2967,

2970 x1 NRZI/Scrambled

SONET-STS-32155.52 x1 N/A

SONET-STS-122622.08 x1 N/A

SONET-STS-4822488 x1 N/A

1. For slower rates, the SERDES are bypassed and CML signals are directly connected to the FPGA routing.

2. The SONET protocol is supported in 8-bit SERDES mode. See TN1176 Lattice ECP3 SERDES/PCS Usage Guide for more information.

sysIO Bank 0 sysIO Bank 1

CH0

CH3

CH2

CH1

SERDES/PCS

Quad D

CH0

CH3

CH2

CH1

CH0

CH3

CH2

CH1

CH0

CH3

CH2

CH1

sysIO Bank 7

sysIO Bank 2

SERDES/PCS

Quad B

SERDES/PCS

Quad A

SERDES/PCS

Quad C

sysIO Bank 6

sysIO Bank 3

Configuration Bank

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

eam, equalize the signal, perform Clock and sing the 8- or 10—bit data to the PCS logic. The i1 data, serialize the data and transmit the serial bit singlerchannel SERDES/PCS block. Each SERDES mit clock to the PCS block and to the FPGA core logic. ES PLL shares the same power supply (VCCA). The output ependent power supplies (VCCOB and VCClB). am for SEHDES/PCS Block i i i i i i . i i i i i i l i i i am pm WM "m pm... i. W W. W aim, m m “ ‘ i mass W55 swag; sERDEs mmn Elock' i i i i i i i i mt ‘ ‘ Polarity Enamel ‘ l3 l l 5mm. l ‘ mm D‘ H D l lﬂl Mm i t D i i ‘ BWass ‘ ‘i‘e 0H m m we PCS As shown in Figure 2741, the PCS receives the parallel dig performs word alignment, decodes (Sb/10b), prowdes Cl domain lrom the recovered clock to the FPGA clock v For the transmit channel, the PCS block receive selects the polarity and passes the 8/10 bit data The PCS also provides bypass modes tha logic. The PCS interface to the FPGA can a the FPGA logic. SCI (SERDES Client Inter

2-46

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

Table 2-14. Available SERDES Quads per LatticeECP3 Devices

SERDES Block

A SERDES receiver channel may receive the serial differential data stream, equalize the signal, perform Clock and

Data Recovery (CDR) and de-serialize the data stream before passing the 8- or 10-bit data to the PCS logic. The

SERDES transmitter channel may receive the parallel 8- or 10-bit data, serialize the data and transmit the serial bit

stream through the differential drivers. Figure 2-41 shows a single-channel SERDES/PCS block. Each SERDES

channel provides a recovered clock and a SERDES transmit clock to the PCS block and to the FPGA core logic.

Each transmit channel, receiver channel, and SERDES PLL shares the same power supply (VCCA). The output

and input buffers of each channel have their own independent power supplies (VCCOB and VCCIB).

Figure 2-41. Simplified Channel Block Diagram for SERDES/PCS Block

PCS

As shown in Figure 2-41, the PCS receives the parallel digital data from the deserializer and selects the polarity,

performs word alignment, decodes (8b/10b), provides Clock Tolerance Compensation and transfers the clock

domain from the recovered clock to the FPGA clock via the Down Sample FIFO.

For the transmit channel, the PCS block receives the parallel data from the FPGA core, encodes it with 8b/10b,

selects the polarity and passes the 8/10 bit data to the transmit SERDES channel.

The PCS also provides bypass modes that allow a direct 8-bit or 10-bit interface from the SERDES to the FPGA

logic. The PCS interface to the FPGA can also be programmed to run at 1/2 speed for a 16-bit or 20-bit interface to

the FPGA logic.

SCI (SERDES Client Interface) Bus

The SERDES Client Interface (SCI) is an IP interface that allows the SERDES/PCS Quad block to be controlled by

registers rather than the configuration memory cells. It is a simple register configuration interface that allows

SERDES/PCS configuration without power cycling the device.

Package ECP3-17 ECP3-35 ECP3-70 ECP3-95 ECP3-150

256 ftBGA 1 1 — — —

484 ftBGA 1111

672 ftBGA—1222

1156 ftBGA — — 3 3 4

HDOUTP

HDOUTN

* 1/8 or 1/10 line rate

Deserializer

1:8/1:10 Word Alignment

8b10b Decoder

Serializer

8:1/10:1

8b10b

Encoder

SERDES PCS

Bypass

Transmitter

Receiver

Recovered Clock*

SERDES Transmit Clock*

Receive Clock

Transmit Clock

SERDES Transmit Clock

Receive Data

Transmit Data

Clock/Data

Recovery Clock

Data

RX_REFCLK

HDINP

HDINN

Equalizer

Bypass

Downsample

FIFO

Upsample

FIFO

Recovered Clock

TX PLL

TX REFCLK

Polarity

Adjust

Polarity

Adjust

CTC

FPGA Core

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

ome additional logic from the ry protocols. Within the same quad, the cking as long as the required clock tree 15 lists the allowable combination of primary ased architecture. For most SERDES settings and stanr ated as a unit. This helps in silicon area savings, better ceECPS quad architecture provides fleXibility: more than one stanr xed and matched within the same quad. In general, the SERDE ther the same or a defined subset of each other, can be supported w ry Protocol column refers to the standard that determines the ref Protocol column shows the other standard that can be supporte so implies that more than two standards in the same quad can b ta rate and reference clock requirements. For example, a quad may 0 Type land Serial Flapile Type II, all in the same quad. ttierCPs Primary and Secondary Protocol Support Primary Protocol Secondary Pro PCI Express 1.1 SGMII PCI Express 1.1 Gigabit Ethernet PCI Express 1.1 Serial Ra PCI Express 1.1 Serial Serial Rapile Type | S Serial Rapile Type | G Serial Rapile Type II Serial Rapile Type ll Serial RapidlD Type ll CPRl-S GG-SDI For further information on SERDES, p IEEE 1149.1 -Complia Lat‘liceECPS SERDES/PCS Usage Guide

2-47

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

The ispLEVER design tools from Lattice support all modes of the PCS. Most modes are dedicated to applications

associated with a specific industry standard data protocol. Other more general purpose modes allow users to

define their own operation. With ispLEVER, the user can define the mode for each quad in a design.

Popular standards such as 10Gb Ethernet, x4 PCI Express and 4x Serial RapidIO can be implemented using IP

(available through Lattice), a single quad (Four SERDES channels and PCS) and some additional logic from the

core.

The LatticeECP3 family also supports a wide range of primary and secondary protocols. Within the same quad, the

LatticeECP3 family can support mixed protocols with semi-independent clocking as long as the required clock fre-

quencies are integer x1, x2, or x11 multiples of each other. Table 2-15 lists the allowable combination of primary

and secondary protocol combinations.

Flexible Quad SERDES Architecture

The LatticeECP3 family SERDES architecture is a quad-based architecture. For most SERDES settings and stan-

dards, the whole quad (consisting of four SERDES) is treated as a unit. This helps in silicon area savings, better

utilization and overall lower cost.

However, for some specific standards, the LatticeECP3 quad architecture provides flexibility; more than one stan-

dard can be supported within the same quad.

Table 2-15 shows the standards can be mixed and matched within the same quad. In general, the SERDES stan-

dards whose nominal data rates are either the same or a defined subset of each other, can be supported within the

same quad. In Table 2-15, the Primary Protocol column refers to the standard that determines the reference clock

and PLL settings. The Secondary Protocol column shows the other standard that can be supported within the

same quad.

Furthermore, Table 2-15 also implies that more than two standards in the same quad can be supported, as long as

they conform to the data rate and reference clock requirements. For example, a quad may contain PCI Express 1.1,

SGMII, Serial RapidIO Type I and Serial RapidIO Type II, all in the same quad.

Table 2-15. LatticeECP3 Primary and Secondary Protocol Support

For further information on SERDES, please see TN1176, LatticeECP3 SERDES/PCS Usage Guide.

IEEE 1149.1-Compliant Boundary Scan Testability

All LatticeECP3 devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant Test

Access Port (TAP). This allows functional testing of the circuit board on which the device is mounted through a

serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to

be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test

Primary Protocol Secondary Protocol

PCI Express 1.1 SGMII

PCI Express 1.1 Gigabit Ethernet

PCI Express 1.1 Serial RapidIO Type I

PCI Express 1.1 Serial RapidIO Type II

Serial RapidIO Type I SGMII

Serial RapidIO Type I Gigabit Ethernet

Serial RapidIO Type II SGMII

Serial RapidIO Type II Gigabit Ethernet

Serial RapidIO Type II Serial RapidIO Type I

CPRI-3 CPRI-2 and CPRI-1

3G-SDI HD-SDI and SD-SDI

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

, LatticeECP3 sysCONFIG Usage Guide ration. The Test Access Port (TAP), dualrbyte, byte and serial configuration. ation and the IEEE Standard 1532 my even I/Os used as dedicated pins with the LatticeECPS sysCONFIG Usage Guide for more information lm modes) - Interface to boot PROM memory ort (PCM mode) Islave SPI port (SSPI mode) hXOWI device, providing control and addressmg ready to be conﬁgured using the selected sysCONFIG port. Once a c tive throughout that conﬁguration cycle. The IEEE 1149.1 port ca ing the appropriate command through the TAP port. so support the Slave SPI Interface. In this mode, the FPGA behave e SPI port ol the FPGA to perform readrwrite operations. Configuration Options P3 devices have enhanced configuration features such as: decryptio mage support. TransFR (Transparent Field Reconfiguration) TransFFt I/O (TFR) is a unique Lattice technology that allows u interrupting system operation using a single ispVM comman ing device conﬁguration. This allows the device to be fie downtime. See TN1087, Minimizing System Interruption During Configuration Using TransFR Technology details. Dual-Boot Image Support Dualrboot images are supported for applicat system FPGA. After the system IS running w remotely and stored in a separate loca LatticeECPa can be rerbooted from thi ing download or incorrect version the original backup golden config For more information, pleas , LatticeECP3 sysCONFIG Usage Guide

2-48

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

access port consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage

VCCJ and can operate with LVCMOS3.3, 2.5, 1.8, 1.5 and 1.2 standards.

For more information, please see TN1169, LatticeECP3 sysCONFIG Usage Guide.

Device Configuration

All LatticeECP3 devices contain two ports that can be used for device configuration. The Test Access Port (TAP),

which supports bit-wide configuration, and the sysCONFIG port, support dual-byte, byte and serial configuration.

The TAP supports both the IEEE Standard 1149.1 Boundary Scan specification and the IEEE Standard 1532 In-

System Configuration specification. The sysCONFIG port includes seven I/Os used as dedicated pins with the

remaining pins used as dual-use pins. See TN1169, LatticeECP3 sysCONFIG Usage Guide for more information

about using the dual-use pins as general purpose I/Os.

There are various ways to configure a LatticeECP3 device:

1. JTAG

2. Standard Serial Peripheral Interface (SPI and SPIm modes) - interface to boot PROM memory

3. System microprocessor to drive a x8 CPU port (PCM mode)

4. System microprocessor to drive a serial slave SPI port (SSPI mode)

5. Generic byte wide flash with a MachXO™ device, providing control and addressing

On power-up, the FPGA SRAM is ready to be configured using the selected sysCONFIG port. Once a configuration

port is selected, it will remain active throughout that configuration cycle. The IEEE 1149.1 port can be activated any

time after power-up by sending the appropriate command through the TAP port.

LatticeECP3 devices also support the Slave SPI Interface. In this mode, the FPGA behaves like a SPI Flash device

(slave mode) with the SPI port of the FPGA to perform read-write operations.

Enhanced Configuration Options

LatticeECP3 devices have enhanced configuration features such as: decryption support, TransFR™ I/O and dual-

boot image support.

1. TransFR (Transparent Field Reconfiguration)

TransFR I/O (TFR) is a unique Lattice technology that allows users to update their logic in the field without

interrupting system operation using a single ispVM command. TransFR I/O allows I/O states to be frozen dur-

ing device configuration. This allows the device to be field updated with a minimum of system disruption and

downtime. See TN1087, Minimizing System Interruption During Configuration Using TransFR Technology for

details.

2. Dual-Boot Image Support

Dual-boot images are supported for applications requiring reliable remote updates of configuration data for the

system FPGA. After the system is running with a basic configuration, a new boot image can be downloaded

remotely and stored in a separate location in the configuration storage device. Any time after the update the

LatticeECP3 can be re-booted from this new configuration file. If there is a problem, such as corrupt data dur-

ing download or incorrect version number with this new boot image, the LatticeECP3 device can revert back to

the original backup golden configuration and try again. This all can be done without power cycling the system.

For more information, please see TN1169, LatticeECP3 sysCONFIG Usage Guide.

Soft Error Detect (SED) Support

LatticeECP3 devices have dedicated logic to perform Cycle Redundancy Code (CRC) checks. During configura-

tion, the configuration data bitstream can be checked with the CRC logic block. In addition, the LatticeECP3 device

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

LatticeECPa Soft Error Detection SED) Usage Guide tween the XFlES pin and ground. Device no boundary scan register on the external which is used to derive a Master Clock (MCLK) for con- nd are available to user logic after configuration is come nominally 2.5MHz. Table 216 lists all the available MCLK ted during the design process, the following sequence takes ock frequency of 3.1MHz. a dif1erent master clock frequency. anges to the selected frequency once the clock configuration bits a a master clock frequency, then the configuration bitstream default scillator is available to the user by routing it as an input clock to th of this oscillator for configuration or user mode, please see TN1169 LatticeECPa sysCONr FIG Usage Guide. lectable Master Clack (MCLK) Frequencies During Configur MCLK(MH1) MCLK (MHz) MCLK 2.5‘ 10 4 3.1 13 4.3 15 5.4 20 6.9 26 3.1 9.2 1. Software defaul 3 1MHz, Density Shifting The LatticeECP3 family is designed package have the same pinout. Furth migration from lower density dev lization design targeted for a hi

2-49

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

can also be programmed to utilize a Soft Error Detect (SED) mode that checks for soft errors in configuration

SRAM. The SED operation can be run in the background during user mode. If a soft error occurs, during user

mode (normal operation) the device can be programmed to generate an error signal.

For further information on SED support, please see TN1184, LatticeECP3 Soft Error Detection (SED) Usage

Guide.

External Resistor

LatticeECP3 devices require a single external, 10K ohm ±1% value between the XRES pin and ground. Device

configuration will not be completed if this resistor is missing. There is no boundary scan register on the external

resistor pad.

On-Chip Oscillator

Every LatticeECP3 device has an internal CMOS oscillator which is used to derive a Master Clock (MCLK) for con-

figuration. The oscillator and the MCLK run continuously and are available to user logic after configuration is com-

pleted. The software default value of the MCLK is nominally 2.5MHz. Table 2-16 lists all the available MCLK

frequencies. When a different Master Clock is selected during the design process, the following sequence takes

place:

1. Device powers up with a nominal Master Clock frequency of 3.1MHz.

2. During configuration, users select a different master clock frequency.

3. The Master Clock frequency changes to the selected frequency once the clock configuration bits are received.

4. If the user does not select a master clock frequency, then the configuration bitstream defaults to the MCLK fre-

quency of 2.5MHz.

This internal CMOS oscillator is available to the user by routing it as an input clock to the clock tree. For further

information on the use of this oscillator for configuration or user mode, please see TN1169, LatticeECP3 sysCON-

FIG Usage Guide.

Table 2-16. Selectable Master Clock (MCLK) Frequencies During Configuration (Nominal)

Density Shifting

The LatticeECP3 family is designed to ensure that different density devices in the same family and in the same

package have the same pinout. Furthermore, the architecture ensures a high success rate when performing design

migration from lower density devices to higher density devices. In many cases, it is also possible to shift a lower uti-

lization design targeted for a high-density device to a lower density device. However, the exact details of the final

resource utilization will impact the likelihood of success in each case. An example is that some user I/Os may

become No Connects in smaller devices in the same packge.

MCLK (MHz) MCLK (MHz) MCLK (MHz)

2.5110 41

3.1 13 45

4.3 15 51

5.4 20 55

6.9 26 60

8.1 30 130

9.2 34 —

1. Software default MCLK frequency. Hardware default is

3.1MHz.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

Lattice“ Semiconguctor Corporation 25”C 5" may cause permanent damage to tne devlce Functlonal operation at tne atecl rn tne operatlonal sectlons ot tnis specttlcation rs not lmplled Thermal Management ment rs required. volts ls permltted (or a duratlon or <20ns. 9="" conditions‘="" parameter="" min.="" supply="" voltage="" 1="" 14="" llary="" supply="" voltage,="" terminating="" resistor="" switching="" power="" 3="" 1="" supply="" (serdes)="" pll="" supply="" voltage="" l/o="" driver="" supply="" voltage="" supply="" voltage="" tor="" leee="" 1149.1="" test="" access="" port="" vhef2="" lnput="" reference="" voltage="" termination="" voltage="" junctlon="" temperature,="" commercial="" operatlorl="" d="" junctlon="" temperature,="" industrial="" operation="" ftdes="" external="" power="" supply5="" input="" buffer="" power="" supply="" (1="" 2v)="" v="" cc'h="" lnput="" buffer="" power="" supply="" (1.5v)="" output="" buffer="" power="" supply="" (1.2v="" vccoe="" output="" buffer="" power="" supply="" (1.5v="" vcca="" transmlt.="" recelve,="" pll="" and="" 1="" for="" correct="" operatren,="" all="" supplles="" except="" vref="" an="" usage="" 2="" it="" vccio="" or="" vccj="" rs="" set="" km="" 2%="" they="" must="" be="" come="" nectect="" to="" tne="" same="" power="" supply="" as="" vccau="" see="" recommended="" voltages="" by="" l/o="" standar="" vccaux="" ramp="" rate="" must="" not="" exceed="" it="" not="" used,="" vrr="" should="" be="" lett="" tloatln="" see="" tn1176,="" lattlceecps="" serdes/pcs="" usage="" gulde="" came-w="">

www.latticesemi.com 3-1 DS1021 DC and Switching_01.7

March 2010 Preliminary Data Sheet DS1021

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

Recommended Operating Conditions1

Absolute Maximum Ratings1, 2, 3

1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

2. Compliance with the Lattice Thermal Management document is required.

3. All voltages referenced to GND.

Supply Voltage VCC . . . . . . . . . . . . . . . . . . . -0.5 to 1.32V

Supply Voltage VCCAUX . . . . . . . . . . . . . . . . -0.5 to 3.75V

Supply Voltage VCCJ . . . . . . . . . . . . . . . . . . -0.5 to 3.75V

Output Supply Voltage VCCIO . . . . . . . . . . . -0.5 to 3.75V

Input or I/O Tristate Voltage Applied4. . . . . . -0.5 to 3.75V

Storage Temperature (Ambient) . . . . . . . . . -65 to 150°C

Junction Temperature (Tj) . . . . . . . . . . . . . . . . . . +125°C

4. Overshoot and undershoot of -2V to (VIHMAX + 2) volts is permitted for a duration of <20ns.

Symbol Parameter Min. Max. Units

VCC2Core Supply Voltage 1.14 1.26 V

VCCAUX2, 4 Auxiliary Supply Voltage, Terminating Resistor Switching Power

Supply (SERDES) 3.135 3.465 V

VCCPLL PLL Supply Voltage 3.135 3.465 V

VCCIO2, 3 I/O Driver Supply Voltage 1.14 3.465 V

VCCJ2Supply Voltage for IEEE 1149.1 Test Access Port 1.14 3.465 V

VREF1 and VREF2 Input Reference Voltage 0.5 1.7 V

VTT5Termination Voltage 0.5 1.3125 V

tJCOM Junction Temperature, Commercial Operation 0 85 °C

tJIND Junction Temperature, Industrial Operation -40 100 °C

SERDES External Power Supply6

VCCIB

Input Buffer Power Supply (1.2V) 1.14 1.26 V

Input Buffer Power Supply (1.5V) 1.425 1.575 V

VCCOB

Output Buffer Power Supply (1.2V) 1.14 1.26 V

Output Buffer Power Supply (1.5V) 1.425 1.575 V

VCCA Transmit, Receive, PLL and Reference Clock Buffer Power Supply 1.14 1.26 V

1. For correct operation, all supplies except VREF and VTT must be held in their valid operation range. This is true independent of feature

usage.

2. If VCCIO or VCCJ is set to 1.2V, they must be connected to the same power supply as VCC. If VCCIO or VCCJ is set to 3.3V, they must be con-

nected to the same power supply as VCCAUX.

3. See recommended voltages by I/O standard in subsequent table.

4. VCCAUX ramp rate must not exceed 30mV/µs during power-up when transitioning between 0V and 3.3V.

5. If not used, VTT should be left floating.

6. See TN1176, LatticeECP3 SERDES/PCS Usage Guide for information on board considerations for SERDES power supplies.

LatticeECP3 Family Data Sheet

DC and Switching Characteristics

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

Min. Typ. Max. Units and inputs _ _ 8 mA om P and N inputs driven by CML driver wnh maxwmum anowed VCCOB axlmum Input current. For a167channeldevuce.melota\ mput current would be mA ESD Stress Min. Unils HBM 1000 gh-speed sena‘ and XHES‘ CDM 500 | inputs CDM 400 n me TW device passes CDM tesung at 250V,

3-2

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

Hot Socketing Specifications1, 3, 4

Hot Socketing Requirements1, 2

ESD Performance

Symbol Parameter Condition Min. Typ. Max. Units

IDK_HS2Input or I/O Leakage Current 0 VIN  VIH (Max.) — — +/-1 mA

IDK5Input or I/O Leakage Current 0  VIN < VCCIO ——+/-1mA

VCCIO  VIN  VCCIO + 0.5V — 18 — mA

1. VCC, VCCAUX and VCCIO should rise/fall monotonically.

2. Applicable to general purpose I/O pins in top I/O banks only.

3. IDK is additive to IPU, IPW or IBH.

4. LVCMOS and LVTTL only.

5. Applicable to general purpose I/O pins in left and right I/O banks only.

Description Min. Typ. Max. Units

Input current per SERDES I/O pin when device is powered down and inputs

driven. —— 8mA

1. Assumes the device is powered down, all supplies grounded, both P and N inputs driven by CML driver with maximum allowed VCCOB

(1.575V), 8b10b data, internal AC coupling.

2. Each P and N input must have less than the specified maximum input current. For a 16-channel device, the total input current would be

8mA*16 channels *2 input pins per channel = 256mA

Pin Group ESD Stress Min. Units

All pins HBM 1000 V

All pins except high-speed serial and XRES1CDM 500 V

High-speed serial inputs CDM 400 V

1. The XRES pin on the TW device passes CDM testing at 250V.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

g g — 10 (1A : — 150 (1A g g -30 — -210 (1A g s so — 210 (1A so — — (1A -30 — — uA g g — — 210 (1A g g — — -210 (1A g g (MAX) V(L(MAX) — V(H(M|N) v 1.8M 1.5V, (.2v, — a — pf (.2v, v(o : o to vIH (MAX) .3v, 2.5V, 1.8M 1.5V, (.2v, — 6 — pf (.2v, v(o : u to vIH (MAX) rmgured as an mm! or as an l/O wnn (he output dnver mrslaled, It Is not measured m: are disabled. nounm banks. SMA

3-3

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

DC Electrical Characteristics

Over Recommended Operating Conditions

Symbol Parameter Condition Min. Typ. Max. Units

IIL, IIH1, 4 Input or I/O Low Leakage 0  VIN  (VCCIO - 0.2V) — — 10 µA

IIH1, 3 Input or I/O High Leakage (VCCIO - 0.2V) < VIN  3.6V — — 150 µA

IPU I/O Active Pull-up Current 0  VIN  0.7 VCCIO -30 — -210 µA

IPD I/O Active Pull-down Current VIL (MAX)  VIN  VCCIO 30 — 210 µA

IBHLS Bus Hold Low Sustaining Current VIN = VIL (MAX) 30 — — µA

IBHHS Bus Hold High Sustaining Current VIN = 0.7 VCCIO -30 — — µA

IBHLO Bus Hold Low Overdrive Current 0  VIN  VCCIO ——210µA

IBHHO Bus Hold High Overdrive Current 0  VIN  VCCIO ——-210µA

VBHT Bus Hold Trip Points 0  VIN  VIH (MAX) VIL (MAX) — VIH (MIN) V

C1 I/O Capacitance2 VCCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,

VCC = 1.2V, VIO = 0 to VIH (MAX)

—8—pf

C2 Dedicated Input Capacitance2VCCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,

VCC = 1.2V, VIO = 0 to VIH (MAX)

—6—pf

1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured

with the output driver active. Bus maintenance circuits are disabled.

2. TA 25oC, f = 1.0MHz.

3. Applicable to general purpose I/Os in top and bottom banks.

4. When used as VREF

, maximum leakage= 25µA.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

Typical Units 89.30 mA ECP3-35EA 89.30 mA ECP3-70E 226.30 mA ECP3-70EA 230 60 mA ECPB-QS E 226.30 mA ECP3-95EA 230 60 mA ECP3-150EA 370.80 mA ECP-17EA 28.20 mA ECP3-35EA 28.20 mA ECP3-70E WT ECP3-70EA 30.60 mA ECP3-95E 30.60 mA ECP3-95EA 30.60 m ECP3-150EA 45.70 ECP-1 7EA 0.05 ECP3-35EA 0.03 ECP3-70E 0. \y Cunem (Per PLL) ECP3-70EA o. ECPB-QS E ECP3-95 EA ECP3-1 SOEA ECP-1 7EA ECP3-3 EC Bank Powev Supp‘y Curvenl (Per Bank) EC ICCJ JTAG Power Supply Currenl ICCA Transmxl. Flecewe, PLL and Relerence Clo 1. Far lurlher Inbrmahon on supply cu 2. Assumes aH outputs are mstated. 3‘ 3. Frequency 0 MHZ

3-4

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

LatticeECP3 Supply Current (Standby)1, 2, 3, 4, 5, 6

Over Recommended Operating Conditions

Symbol Parameter Device Typical Units

ICC Core Power Supply Current

ECP-17EA 89.30 mA

ECP3-35EA 89.30 mA

ECP3-70E 226.30 mA

ECP3-70EA 230.60 mA

ECP3-95E 226.30 mA

ECP3-95EA 230.60 mA

ECP3-150EA 370.80 mA

ICCAUX Auxiliary Power Supply Current

ECP-17EA 28.20 mA

ECP3-35EA 28.20 mA

ECP3-70E 30.60 mA

ECP3-70EA 30.60 mA

ECP3-95E 30.60 mA

ECP3-95EA 30.60 mA

ECP3-150EA 45.70 mA

ICCPLL PLL Power Supply Current (Per PLL)

ECP-17EA 0.05 mA

ECP3-35EA 0.03 mA

ECP3-70E 0.02 mA

ECP3-70EA 0.02 mA

ECP3-95E 0.02 mA

ECP3-95EA 0.02 mA

ECP3-150EA 0.02 mA

ICCIO Bank Power Supply Current (Per Bank)

ECP-17EA 1.38 mA

ECP3-35EA 1.38 mA

ECP3-70E 1.43 mA

ECP3-70EA 1.43 mA

ECP3-95E 1.43 mA

ECP3-95EA 1.43 mA

ECP3-150EA 1.46 mA

ICCJ JTAG Power Supply Current All Devices 2.50 mA

ICCA Transmit, Receive, PLL and Reference Clock Buffer Power Supply

ECP-17EA 5.90 mA

ECP3-35EA 5.90 mA

ECP3-70E 17.80 mA

ECP3-70EA 17.80 mA

ECP3-95E 17.80 mA

ECP3-95EA 17.80 mA

ECP3-150EA 23.80 mA

1. For further information on supply current, please see the list of technical documentation at the end of this data sheet.

2. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the VCCIO or GND.

3. Frequency 0 MHz.

4. Pattern represents a “blank” configuration data file.

5. TJ = 85°C, power supplies at nominal voltage.

6. To determine the LatticeECP3 peak start-up current data, use the Power Calculator tool in ispLEVER.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

5 mA — mA — mA 68 77 mA 5 7 mA 19 25 mA 66 76 mA channel) 4 5 mA nl (per channel) 15 18 mA (per channel) 62 72 mA buller currenl (per channel) 4 5 mA Oulpul buffer currenl (per channel) 15 18 mA 0 Mbps) VCCA currenl (per channel) 55 65 lnpul buller current (per channel) 4 5 Oulpul buffer currenl (per channel) 14 17 nabledl preemphasus dlsabled. er at me mlal quad power lmcludes contribution lrom common clrculls‘ all chann mphasus disabledl equallzauen enabled). empnaSls adds ZUmA (o ICCAVOF dala

3-5

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

SERDES Power Supply Requirements1, 2, 3

Over Recommended Operating Conditions

Symbol Description Typ. Max. Units

Standby (Power Down)

ICCA-SB VCCA current (per channel) 3 5 mA

ICCIB-SB Input buffer current (per channel) — — mA

ICCOB-SB Output buffer current (per channel) — — mA

Operating (Data Rate = 3.2 Gbps)

ICCA-OP VCCA current (per channel) 68 77 mA

ICCIB-OP Input buffer current (per channel) 5 7 mA

ICCOB-OP Output buffer current (per channel) 19 25 mA

Operating (Data Rate = 2.5 Gbps)

ICCA-OP VCCA current (per channel) 66 76 mA

ICCIB-OP Input buffer current (per channel) 4 5 mA

ICCOB-OP Output buffer current (per channel) 15 18 mA

Operating (Data Rate = 1.25 Gbps)

ICCA-OP VCCA current (per channel) 62 72 mA

ICCIB-OP Input buffer current (per channel) 4 5 mA

ICCOB-OP Output buffer current (per channel) 15 18 mA

Operating (Data Rate = 250 Mbps)

ICCA-OP VCCA current (per channel) 55 65 mA

ICCIB-OP Input buffer current (per channel) 4 5 mA

ICCOB-OP Output buffer current (per channel) 14 17 mA

1. Equalization enabled, pre-emphasis disabled.

2. One quarter of the total quad power (includes contribution from common circuits, all channels in the quad operating,

pre-emphasis disabled, equalization enabled).

3. Pre-emphasis adds 20mA to ICCA-OP data.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

7 1.89 2.625 3.465 1.575 8 1.89 2 5 2.625 2 5 2.625 3 3 3.465 2.375 2 5 2.625 2.375 2 5 2.625 2.375 2 5 2.625 3.14 3 3 3.47 3.14/2.25 3.3/2.5 347/275 1.43 1 5 1.57 SSTL1BDJ . H 1.71 1 8 1.89 SSTL25D, 1 . H 2.375 2 5 2.625 SSTL33D, ‘2. H2 3.135 3 3 3.465 TL15D,‘ 1.425 1 5 1.575 TL18D,1,I| 1.71 1.8 1.8 1. Inputs an amp. Outputs are \mplememed wnn me addmon or externa‘ reswsto 2. Far mpul voltage compatibmly. reler m me "Mxxed Voltage Suppan" se LamceECPa sys‘O Usage Game

3-6

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

sysI/O Recommended Operating Conditions

Standard

VCCIO VREF (V)

Min. Typ. Max. Min. Typ. Max.

LVCM OS332 3.135 3.3 3.465 — — —

LVCM OS2 52 2.375 2.5 2.625 — — —

LVCMOS18 1.71 1.8 1.89 — — —

LVCMOS15 1.425 1.5 1.575 — — —

LVCM OS1 22 1.14 1.2 1.26 — — —

LVTT L33 2 3.135 3.3 3.465 — — —

PCI33 3.135 3.3 3.465 — — —

SSTL1531.43 1.5 1.57 0.68 0.75 0.9

SSTL18_I, II21.71 1.8 1.89 0.833 0.9 0.969

SSTL25_I, II22.375 2.5 2.625 1.15 1.25 1.35

SSTL33_I, II23.135 3.3 3.465 1.3 1.5 1.7

HSTL15_I21.425 1.5 1.575 0.68 0.75 0.9

HSTL18_I, II21.71 1.8 1.89 0.816 0.9 1.08

LVDS 252 2.375 2.5 2.625 — — —

MLVDS251 2.375 2.5 2.625 — — —

LVPECL331, 2 3.135 3.3 3.465 — — —

Mini LVDS ——————

BLVDS251, 2 2.375 2.5 2.625 — — —

RSDS251, 2 2.375 2.5 2.625 — — —

RSDS25E1, 2 2.375 2.5 2.625 — — —

TRLVDS 3.14 3.3 3.47 — — —

PPLVDS 3.14/2.25 3.3/2.5 3.47/2.75 — — —

SSTL15D 1.43 1.5 1.57 — — —

SSTL18D_I2, II21.71 1.8 1.89 — — —

SSTL25D_ I2, II22.375 2.5 2.625 — — —

SSTL33D_ I2, II23.135 3.3 3.465 — — —

HSTL15D_ I21.425 1.5 1.575 — — —

HSTL18D_ I2, II21.71 1.8 1.89 — — —

1. Inputs on chip. Outputs are implemented with the addition of external resistors.

2. For input voltage compatibility, refer to the "Mixed Voltage Support" section of TN1177, LatticeECP3 sysIO Usage Guide.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

20,16, -20. -16. 12.8.4 -12.-6.-4 10-02 0.1 -0.1 20.16, -20. -16. VCG‘O ' 0'4 12, 8, 4 -12. -8. -4 .2 cho-D-Z 0.1 16,121 0.4 vow-0.4 8,4 0.2 vow-0.2 0.1 0.4 v -0.4 8,4 3.6 CC‘O 0.2 cho-O-Z 0.1 36 0.4 vow-0.4 6,2 ' 0.2 cho-O-Z 0.1 . 20,16, -20. -16. 20 3.6 0.4 vow-0.4 1284 _12‘_ 0.2 cho-O-Z 0.1 0.5 cho 3.6 01 V0010 0.9cho 1.5 -0.125 VHEF+D.125 3.6 0.4 vow-0.4 6.7 8 F-0.125 VHEF+0.125 3.6 0.28 vow-0.28 11 VHEF-ma VHEF+0.1B 3.6 0.54 vow-0.62 -0.3 VHEF-0.18 VHEF+0.18 3.6 0.35 cho-0 -0.3 VHEF-O.2 VHEF+0.2 3.6 0.7 v0 -0.3 VHEF-02 VHEF+0.2 3.6 0.5 SSTL15 (DDRSMemmy) -0.3 VHEF-m VHEF+0.1 3.6 0.3 HSTL15J -0.3 VHEF-m VHEF+0.1 3.6 HSTL18J -0.3 VHEF-m VHEF+0.1 3. HSTL187|| -0.3 VHEF-m VHEF+0.1 1. The average DC currem drawn by l/Os be1ween GND con shown 1nmelog1c sugna1 connecmnstable shan n01 exce between me ‘35! GND m a bank and the end 0! a bank.

3-7

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

sysI/O Single-Ended DC Electrical Characteristics

Input/Output

Standard

VIL VIH VOL

Max. (V)

VOH

Min. (V) IOL1 (mA) IOH1 (mA)Min. (V) Max. (V) Min. (V) Max. (V)

LVCMOS33 -0.3 0.8 2.0 3.6 0.4 VCCIO - 0.4 20, 16,

12, 8, 4

-20, -16,

-12, -8, -4

0.2 VCCIO - 0.2 0.1 -0.1

LVCMOS25 -0.3 0.7 1.7 3.6 0.4 VCCIO - 0.4 20, 16,

12, 8, 4

-20, -16,

-12, -8, -4

0.2 VCCIO - 0.2 0.1 -0.1

LVCMOS18 -0.3 0.35 VCCIO 0.65 VCCIO 3.6 0.4 VCCIO - 0.4 16, 12,

8, 4

-16, -12,

-8, -4

0.2 VCCIO - 0.2 0.1 -0.1

LVCMOS15 -0.3 0.35 VCCIO 0.65 VCCIO 3.6 0.4 VCCIO - 0.4 8, 4 -8, -4

0.2 VCCIO - 0.2 0.1 -0.1

LVCMOS12 -0.3 0.35 VCC 0.65 VCC 3.6 0.4 VCCIO - 0.4 6, 2 -6, -2

0.2 VCCIO - 0.2 0.1 -0.1

LVTTL33 -0.3 0.8 2.0 3.6 0.4 VCCIO - 0.4 20, 16,

12, 8, 4

-20, -16,

-12, -8, -4

0.2 VCCIO - 0.2 0.1 -0.1

PCI33 -0.3 0.3 VCCIO 0.5 VCCIO 3.6 0.1 VCCIO 0.9 VCCIO 1.5 -0.5

SSTL18_I -0.3 VREF - 0.125 VREF + 0.125 3.6 0.4 VCCIO - 0.4 6.7 -6.7

SSTL18_II

(DDR2 Memory) -0.3 VREF - 0.125 VREF + 0.125 3.6 0.28 VCCIO - 0.28 8-8

11 -11

SSTL2_I -0.3 VREF - 0.18 VREF + 0.18 3.6 0.54 VCCIO - 0.62 7.6 -7.6

12 -12

SSTL2_II

(DDR2 Memory) -0.3 VREF - 0.18 VREF + 0.18 3.6 0.35 VCCIO - 0.43 15.2 -15.2

20 -20

SSTL3_I -0.3 VREF - 0.2 VREF + 0.2 3.6 0.7 VCCIO - 1.1 8 -8

SSTL3_II -0.3 VREF - 0.2 VREF + 0.2 3.6 0.5 VCCIO - 0.9 16 -16

SSTL15

(DDR3 Memory) -0.3 VREF - 0.1 VREF + 0.1 3.6 0.3 VCCIO - 0.3 7.5 -7.5

VCCIO * 0.8 9 -9

HSTL15_I -0.3 VREF - 0.1 VREF + 0.1 3.6 0.4 VCCIO - 0.4 4-4

8-8

HSTL18_I -0.3 VREF - 0.1 VREF + 0.1 3.6 0.4 VCCIO - 0.4 8-8

12 -12

HSTL18_II -0.3 VREF - 0.1 VREF + 0.1 3.6 0.4 VCCIO - 0.4 16 -16

1. The average DC current drawn by I/Os between GND connections, or between the last GND in an I/O bank and the end of an I/O bank, as

shown in the logic signal connections table shall not exceed n * 8mA, where n is the number of I/Os between bank GND connections or

between the last GND in a bank and the end of a bank.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

Min. Typ. Max. Units — 2.4 V 0.05 — 2.35 V Inpu1s +/—100 — — mV — — +/-1o pA — 1.38 1.60 V 0.9V 1.03 — V 100 Ohm 250 350 450 mV — — 50 mV VOW/2, FlT : 100 Ohm 1.125 1.20 1.375 V — — 50 mV VOD : 0V Driver Outputs Shoned m _ _ Each Other 12 mA are \mplememed as a pair of complememary single»ended oulpu class I and class II) are supponed in this mode.

3-8

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

sysI/O Differential Electrical Characteristics

LVD S2 5

Over Recommended Operating Conditions

Differential HSTL and SSTL

Differential HSTL and SSTL outputs are implemented as a pair of complementary single-ended outputs. All allow-

able single-ended output classes (class I and class II) are supported in this mode.

Parameter Description Test Conditions Min. Typ. Max. Units

VINP

, VINM Input Voltage 0 — 2.4 V

VCM Input Common Mode Voltage Half the Sum of the Two Inputs 0.05 — 2.35 V

VTHD Differential Input Threshold Difference Between the Two Inputs +/-100 — — mV

IIN Input Current Power On or Power Off — — +/-10 µA

VOH Output High Voltage for VOP or VOM RT = 100 Ohm — 1.38 1.60 V

VOL Output Low Voltage for VOP or VOM RT = 100 Ohm 0.9V 1.03 — V

VOD Output Voltage Differential (VOP - VOM), RT = 100 Ohm 250 350 450 mV

VOD Change in VOD Between High and

Low ——50mV

VOS Output Voltage Offset (VOP + VOM)/2, RT = 100 Ohm 1.125 1.20 1.375 V

VOS Change in VOS Between H and L — — 50 mV

ISAB Output Short Circuit Current VOD = 0V Driver Outputs Shorted to

Each Other ——12mA

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

hms RT : 100 ohms (:i we) DE} \ i ime, Zo : Ion ohm dillerenllal OFFrchip l ONrchlp Description Typical Units Output Driver Suppiy (+/-5%) 2.50 V iver Impedance 20 0 Driver Series Resistor (+/-1%) 158 0 Driver Parallel Resistor (+/—1%) 140 Q Receiver Termination (+/-1%) 100 Q VOH Output High Voitage 1.43 VOL Output Low Voltage 1.07 Von Output Differential Voltage 0.35 VCM Output Common Mode Voltage 1. ZEN;K Back Impedance 10 0 'DC DC Output Current LVCMOS33D Ail I/O banks suppori emulated diﬂerentiai IIO using me LVC resistor network, provides the system designer ihe fiexibiiit VCC‘O. The defauit drive current for LVCMOSSSD out 4mA, BmA, 16mA or 20mA. Follow the LVCMOS

3-9

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

LVDS25E

The top and bottom sides of LatticeECP3 devices support LVDS outputs via emulated complementary LVCMOS

outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3-1 is one

possible solution for point-to-point signals.

Figure 3-1. LVDS25E Output Termination Example

Table 3-1. LVDS25E DC Conditions

LVCMOS33D

All I/O banks support emulated differential I/O using the LVCMOS33D I/O type. This option, along with the external

resistor network, provides the system designer the flexibility to place differential outputs on an I/O bank with 3.3V

VCCIO. The default drive current for LVCMOS33D output is 12mA with the option to change the device strength to

4mA, 8mA, 16mA or 20mA. Follow the LVCMOS33 specifications for the DC characteristics of the LVCMOS33D.

Parameter Description Typical Units

VCCIO Output Driver Supply (+/-5%) 2.50 V

ZOUT Driver Impedance 20 

RSDriver Series Resistor (+/-1%) 158 

RPDriver Parallel Resistor (+/-1%) 140 

RTReceiver Termination (+/-1%) 100 

VOH Output High Voltage 1.43 V

VOL Output Low Voltage 1.07 V

VOD Output Differential Voltage 0.35 V

VCM Output Common Mode Voltage 1.25 V

ZBACK Back Impedance 100.5 

IDC DC Output Current 6.03 mA

RS=158 ohms

(±1%)

RS=158 ohms

(±1%)

RP = 140 ohms

(±1%)

RT = 100 ohms

(±1%)

OFF-chip

Transmission line, Zo = 100 ohm differential

VCCIO = 2.5V (±5%)

8 mA

VCCIO = 2.5V (±5%)

ON-chip OFF-chip ON-chip

8 mA

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

rrerentral stv 25V 4L C Conditions’ Over Recommended Operating Cond ons Typical Parameter Description 20 = 450 900 Vcclo Output Driver Supply (+/- 5%) 2.50 ZouT Driver impedance 10.00 0 R5 Driver Series Resistor (+/- 1%) ﬂ RTL Driver Parallel Resistor (+/- 1%) 0 Ram Receiver Termination (+/- 1%) ﬂ VOH Output High Voltage VOL Output Low Voltage Von Output Ditlerenlral Voltage VCM Output Common Mode '05 DC Output Current 1, For Input butter, see LVDS table

3-10

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

BLVDS25

The LatticeECP3 devices support the BLVDS standard. This standard is emulated using complementary LVCMOS

outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when

multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-2 is one

possible solution for bi-directional multi-point differential signals.

Figure 3-2. BLVDS25 Multi-point Output Example

Table 3-2. BLVDS25 DC Conditions1

Over Recommended Operating Conditions

Parameter Description

Typical

UnitsZo = 45Zo = 90

VCCIO Output Driver Supply (+/- 5%) 2.50 2.50 V

ZOUT Driver Impedance 10.00 10.00 

RSDriver Series Resistor (+/- 1%) 90.00 90.00 

RTL Driver Parallel Resistor (+/- 1%) 45.00 90.00 

RTR Receiver Termination (+/- 1%) 45.00 90.00 

VOH Output High Voltage 1.38 1.48 V

VOL Output Low Voltage 1.12 1.02 V

VOD Output Differential Voltage 0.25 0.46 V

VCM Output Common Mode Voltage 1.25 1.25 V

IDC DC Output Current 11.24 10.20 mA

1. For input buffer, see LVDS table.

Heavily loaded backplane, effective Zo ~ 45 to 90 ohms differential

2.5V

RTL RTR

RS = 90 ohms

RS = 90 ohms RS =

90 ohms

RS =

90 ohms RS =

90 ohms

RS =

90 ohms

RS =

90 ohms

RS =

90 ohms

45-90

ohms

45-90

ohms

2.5V

2.5V 2.5V 2.5V 2.5V

2.5V

. . .

16mA

16mA 16mA 16mA 16mA

16mA

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

16mA D‘ V o: 3 ohms RT: 100 ohms i 1 (+/75% 1 w (471% 1 16“ D1 Transmission iine, 1 1 Z0 : 100 ohm dilferentlal V 1 Onrc ‘ Ollrcmp ‘ Ourchlp 471% 471% Over Recommended Operating Can one Description Typical Units Output Driver Supply (+l-5°/u) 3.30 V ZOUT Driver impedance 10 0 R5 Driver Series Resistor (+/—1%) 93 0 RF. Driver Parallel Resistor (+l-1%) 196 0 RT Receiver Termination (+l-1%) 10 ﬂ VOH Output High Voltage 2.0 VOL Output Low Voilage Von Output Differential Voltage VCM Output Common Mode Voltage ZEN;K Back impedance 0 'Dc DC Output Current 1, For input butler, see LVDS table

3-11

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

LVPECL33

The LatticeECP3 devices support the differential LVPECL standard. This standard is emulated using complemen-

tary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input standard

is supported by the LVDS differential input buffer. The scheme shown in Figure 3-3 is one possible solution for

point-to-point signals.

Figure 3-3. Differential LVPECL33

Table 3-3. LVPECL33 DC Conditions1

Over Recommended Operating Conditions

Parameter Description Typical Units

VCCIO Output Driver Supply (+/-5%) 3.30 V

ZOUT Driver Impedance 10 

RSDriver Series Resistor (+/-1%) 93 

RPDriver Parallel Resistor (+/-1%) 196 

RTReceiver Termination (+/-1%) 100 

VOH Output High Voltage 2.05 V

VOL Output Low Voltage 1.25 V

VOD Output Differential Voltage 0.80 V

VCM Output Common Mode Voltage 1.65 V

ZBACK Back Impedance 100.5 

IDC DC Output Current 12.11 mA

1. For input buffer, see LVDS table.

Transmission line,

Zo = 100 ohm differential

Off-chipOn-chip

VCCIO = 3.3V

(+/-5%)

VCCIO = 3.3V

(+/-5%)

RP = 196 ohms

(+/-1%) RT = 100 ohms

(+/-1%)

RS = 93.1 ohms

(+/-1%)

RS = 93.1 ohms

(+/-1%)

16mA

Off-chip On-chip

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

d values ior 1% resisiors. (+/75°a l l 8mA D‘ ‘ VCCiO= 1 ms RT: 100 ohms 1 1mm 1 we) (+H %) 1 ‘ 8mA D V . . 1 Transmission me, 1 r Zo =100 ohm diﬂerenliai r Onrch 1 Oil-Chip 1 On~chip <7 ‘4»="" 47‘="" over="" recommended="" operaiing="" can="" one="" descriplion="" typical="" units="" ouipui="" driver="" supply="" (+l-5%)="" 2.50="" v="" ut="" driver="" impedance="" 20="" q="" rs="" driver="" series="" resistor="" (+/-1%)="" 294="" q="" rp="" driver="" paraiiei="" resistor="" (+l-1%)="" 121="" q="" rt="" receiver="" termination="" (+l-1%)="" 100="" q="" voh="" ouipur="" high="" voltage="" 1.35="" vol="" ouiput="" low="" voiiage="" vod="" ouipui="" differeniial="" voliage="" vcm="" ouipur="" common="" mode="" voliage="" zhack="" back="" impedance="" q="" ‘06="" dc="" output="" currenr="" i.="" for="" inpul="" burrer‘="" see="" lvds="" table,="">

3-12

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

RSDS25E

The LatticeECP3 devices support differential RSDS and RSDSE standards. This standard is emulated using com-

plementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The RSDS input stan-

dard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-4 is one possible solution for

RSDS standard implementation. Resistor values in Figure 3-4 are industry standard values for 1% resistors.

Figure 3-4. RSDS25E (Reduced Swing Differential Signaling)

Table 3-4. RSDS25E DC Conditions1

Over Recommended Operating Conditions

Parameter Description Typical Units

VCCIO Output Driver Supply (+/-5%) 2.50 V

ZOUT Driver Impedance 20 

RSDriver Series Resistor (+/-1%) 294 

RPDriver Parallel Resistor (+/-1%) 121 

RTReceiver Termination (+/-1%) 100 

VOH Output High Voltage 1.35 V

VOL Output Low Voltage 1.15 V

VOD Output Differential Voltage 0.20 V

VCM Output Common Mode Voltage 1.25 V

ZBACK Back Impedance 101.5 

IDC DC Output Current 3.66 mA

1. For input buffer, see LVDS table.

= 294 ohms

(+/-1%)

= 294 ohms

(+/-1%)

= 121 ohms

(+/-1%)

= 100 ohms

(+/-1%)

On-chip On-chip

8mA

VCCIO = 2.5V

(+/-5%)

VCCIO = 2.5V

(+/-5%)

Transmission line,

Zo = 100 ohm differential

Off-chipOff-chip

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

vaiues for 1% resistors. .mm 15mm so m m ohm: w 1% an 353;.“ j Egan. 323:... : LA LA T L 1: 0E . , 25v oE 1,5v 175 ram lama mm Iions’ Typical Parameter Description Zo=50Q Zo=70Q Output Driver Supply (+/-5°/=) 2.50 2.50 our Driver Impedance 10.00 10.00 Q Rs Driver Series Resistor (+/-1%) 35.00 Q RTL Driver Parallel Resistor (+/-1%) 50.00 Q Rm Receiver Termination (+/-1%) 50.00 Q VOH Output High Voitage V0L Output Low Voltage VOD Output Differential Voltage VCM Output Common Mode Voltage ‘00 DC Output Current 1. For input butter. see LVDS tabie,

3-13

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

MLVDS25

The LatticeECP3 devices support the differential MLVDS standard. This standard is emulated using complemen-

tary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The MLVDS input standard is

supported by the LVDS differential input buffer. The scheme shown in Figure 3-5 is one possible solution for

MLVDS standard implementation. Resistor values in Figure 3-5 are industry standard values for 1% resistors.

Figure 3-5. MLVDS25 (Multipoint Low Voltage Differential Signaling)

Table 3-5. MLVDS25 DC Conditions1

Parameter Description

Typical

UnitsZo=50Zo=70

VCCIO Output Driver Supply (+/-5%) 2.50 2.50 V

ZOUT Driver Impedance 10.00 10.00 

RSDriver Series Resistor (+/-1%) 35.00 35.00 

RTL Driver Parallel Resistor (+/-1%) 50.00 70.00 

RTR Receiver Termination (+/-1%) 50.00 70.00 

VOH Output High Voltage 1.52 1.60 V

VOL Output Low Voltage 0.98 0.90 V

VOD Output Differential Voltage 0.54 0.70 V

VCM Output Common Mode Voltage 1.25 1.25 V

IDC DC Output Current 21.74 20.00 mA

1. For input buffer, see LVDS table.

16mA

2.5V

Am61

Heavily loaded backplace, effective Zo~50 to 70 ohms differential

50 to 70 ohms +/-1%

RS =

35ohms

RS =

35ohms

RS =

35ohms

RS =

35ohms

RS =

35ohms

RS =

35ohms

RS =

35ohms

RTR

RTL

16mA

2.5V

Am61

2.5V

Am61

2.5V 2.5V

RS =

50 to 70 ohms +/-1%

35ohms

Am61

16mA

OE OE OE OE

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

47 ns 47 ns 57 ns 4.1 ns 4.3 ns 4.7 ns 4.8 ns cl perinrmance may vary wun device and iooi versmn. The tool uses n every meme. e iypicaHy smwer and can be extracted from (he ispLEVER soﬂware -8 Timing Units 500 MH 500 475 500 500 50 er counier i counier 64-bii counier 64-bii accumulator Embedded Memory Functions 512x36 Single Port RAM. EBR Outpui Regisiers 1024x18 True-Duai Povt RAM (Wriie Through or Normal, E 1024x18 True-Duai Pen RAM (Read-Before-inie, EBR Ou only) 1024x18 True-Dual Port RAM (Wriie Through or Norm Distributed Memory Functions 16x4 Pseudo-Dual Port RAM (One PFU) 32x4 Pseudo-Dual Port RAM 64x8 Pseudo-Dual Pori RAM DSP Function

3-14

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

Typical Building Block Function Performance

Pin-to-Pin Performance (LVCMOS25 12mA Drive)1, 2

Function -8 Timing Units

Basic Functions

16-bit Decoder 4.7 ns

32-bit Decoder 4.7 ns

64-bit Decoder 5.7 ns

4:1 MUX 4.1 ns

8:1 MUX 4.3 ns

16:1 MUX 4.7 ns

32:1 MUX 4.8 ns

1. These functions were generated using the ispLEVER design tool. Exact performance may vary with device and tool version. The tool uses

internal parameters that have been characterized but are not tested on every device.

2. Commercial timing numbers are shown. Industrial numbers are typically slower and can be extracted from the ispLEVER software.

Function -8 Timing Units

Basic Functions

16-bit Decoder 500 MHz

32-bit Decoder 500 MHz

64-bit Decoder 475 MHz

4:1 MUX 500 MHz

8:1 MUX 500 MHz

16:1 MUX 500 MHz

32:1 MUX 445 MHz

8-bit adder 500 MHz

16-bit adder 500 MHz

64-bit adder 305 MHz

16-bit counter 500 MHz

32-bit counter 460 MHz

64-bit counter 320 MHz

64-bit accumulator 315 MHz

Embedded Memory Functions

512x36 Single Port RAM, EBR Output Registers 340 MHz

1024x18 True-Dual Port RAM (Write Through or Normal, EBR Output Registers) 340 MHz

1024x18 True-Dual Port RAM (Read-Before-Write, EBR Output Registers; EA devices

only) 130 MHz

1024x18 True-Dual Port RAM (Write Through or Normal, PLC Output Registers) 245 MHz

Distributed Memory Functions

16x4 Pseudo-Dual Port RAM (One PFU) 500 MHz

32x4 Pseudo-Dual Port RAM 500 MHz

64x8 Pseudo-Dual Port RAM 380 MHz

DSP Function

18x18 Multiplier (All Registers) 400 MHz

9x9 Multiplier (All Registers) 400 MHz

36x36 Multiply (All Registers) 245 MHz

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

MHZ MHZ MHZ ay vary with devrce and mi version. The tool uses Interr and can be eximcied irom me IspLEVER soiiware a sheer and the ispLEVER design ioois are worst case minai Iemperaiure and voltage for best case process, can be e ispLEVER design iool can provide logic liming numbers at a

3-15

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

, 2

Derating Timing Tables

Logic timing provided in the following sections of this data sheet and the ispLEVER design tools are worst case

numbers in the operating range. Actual delays at nominal temperature and voltage for best case process, can be

much better than the values given in the tables. The ispLEVER design tool can provide logic timing numbers at a

particular temperature and voltage.

18x18 Multiply/Accumulate (Input & Output Registers) 200 MHz

18x18 Multiply-Add/Sub (All Registers) 400 MHz

DSP IP Functions

16-Tap Fully-Parallel FIR Filter MHz

1024-pt, Radix 4, Decimation in Frequency FFT MHz

8X8 Matrix Multiplication MHz

1. These timing numbers were generated using ispLEVER tool. Exact performance may vary with device and tool version. The tool uses inter-

nal parameters that have been characterized but are not tested on every device.

2. Commercial timing numbers are shown. Industrial numbers are typically slower and can be extracted from the ispLEVER software.

Function -8 Timing Units

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

-7 -6 Max. Min. Max. Units — 500 — 420 — 375 MHZ 0.8 — 0.9 — 1.0 — ns — 300 — 330 — 360 p5 ECPS-ISOEA — 250 — 280 — 300 p5 ECP3-7OE/95E — 500 — 420 — 375 MHZ ECP3-7OE/95E 0.8 — 0.9 — 1.0 — ns ECP3-7OE/95E — 300 — 330 — 360 p5 ECP3-7DE/95E — 250 — 280 — 300 p5 ECPS-ISOEA — 500 — 420 — 375 Clock ECFS-ISOEA 0.9 — 1.0 — 1.2 — 5” Edge °' ECF3-150EA — zoo — 21o — Clock ECP3-7DE/95E — 500 — 420 Ise WIdIh Ior Edge Clock ECP3-7OE/95E 0.9 — 1.0 — CIock Skew Within an Edge oi ECP3-70E/95E _ 200 _ 2 Devuce Description Device SDR I0 Fin Parameters Using Dedicated Clock Input Primary Clock With Clock to Output - PIO Output Ftegxster ECP3-150EA — glrock to Data Setup - PIO Input Regis- ECP3-150EA ‘H :3ch to Data Hold - PIO Input Ftegvs- ECP3-1 ‘ Clock to Data Setup - PIO Input Regis- E squL ter with Data Input Delay ‘ Clock to Data HoId - PIO Input Ftegxs- ”DEL ter with Input Data Delay f Clock Frequency of I/O and PFU Ft ”W90 ister tco Clock to Output - PIO Output Clock to Data Setup - P ‘su ter Clock to Data Ho ter

3-16

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

LatticeECP3 External Switching Characteristics 1, 2

Over Recommended Commercial Operating Conditions

Parameter Description Device

-8 -7 -6

UnitsMin. Max. Min. Max. Min. Max.

Clocks

Primary Clock6

fMAX_PRI Frequency for Primary Clock Tree ECP3-150EA —500 —420 —375 MHz

tW_PRI Clock Pulse Width for Primary Clock ECP3-150EA 0.8 —0.9 —1.0 —ns

tSKEW_PRI Primary Clock Skew Within a Device ECP3-150EA —300 —330 —360 ps

tSKEW_PRIB Primary Clock Skew Within a Bank ECP3-150EA —250 —280 —300 ps

tW_PRI Frequency for Primary Clock Tree ECP3-70E/95E — 500 — 420 — 375 MHz

fMAX_PRI Frequency for Primary Clock Tree ECP3-70E/95E 0.8 — 0.9 — 1.0 — ns

tSKEW_PRI Primary Clock Skew Within a Device ECP3-70E/95E — 300 — 330 — 360 ps

tSKEW_PRIB Primary Clock Skew Within a Bank ECP3-70E/95E — 250 — 280 — 300 ps

Edge Clock6

fMAX_EDGE Frequency for Edge Clock ECP3-150EA —500 —420 —375 MHz

tW_EDGE Clock Pulse Width for Edge Clock ECP3-150EA 0.9 —1.0 —1.2 —ns

tSKEW_EDGE_DQS Edge Clock Skew Within an Edge of

the Device ECP3-150EA —200 —210 —220 ps

fMAX_EDGE Frequency for Edge Clock ECP3-70E/95E — 500 — 420 — 375 MHz

tW_EDGE Clock Pulse Width for Edge Clock ECP3-70E/95E 0.9 — 1.0 — 1.2 — ns

tSKEW_EDGE_DQS Edge Clock Skew Within an Edge of

the Device ECP3-70E/95E — 200 — 225 — 250 ps

Parameter Description Device

-8 -7 -6

UnitsMin. Max. Min. Max. Min. Max.

Generic SDR

General I/O Pin Parameters Using Dedicated Clock Input Primary Clock Without PLL2

tCO Clock to Output - PIO Output Register ECP3-150EA —4.0 —4.4 —4.8 ns

tSU Clock to Data Setup - PIO Input Regis-

ter ECP3-150EA 0.0 —0.0 —0.0 —ns

tHClock to Data Hold - PIO Input Regis-

ter ECP3-150EA 1.6 —1.8 —2.1 —ns

tSU_DEL Clock to Data Setup - PIO Input Regis-

ter with Data Input Delay ECP3-150EA 1.2 —1.3 —1.5 —ns

tH_DEL Clock to Data Hold - PIO Input Regis-

ter with Input Data Delay ECP3-150EA 0.1 —0.1 —0.1 —ns

fMAX_IO Clock Frequency of I/O and PFU Reg-

ister ECP3-150EA —500 —420 —375 MHz

tCO Clock to Output - PIO Output Register ECP3-70E/95E — 3.9 — 4.3 -— 4.7 ns

tSU Clock to Data Setup - PIO Input Regis-

ter ECP3-70E/95E 0.0 — 0.0 — 0.0 — ns

tHClock to Data Hold - PIO Input Regis-

ter ECP3-70E/95E 1.5 — 1.8 — 2.0 — ns

tSU_DEL Clock to Data Setup - PIO Input Regis-

ter with Data Input Delay ECP3-70E/95E 1.3 — 1.5 — 1.8 — ns

tH_DEL Clock to Data Hold - PIO Input Regis-

ter with Input Data Delay ECP3-70E/95E 0.0 — 0.0 — 0.0 — ns

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

Max. Min. Max. Units 420 — 375 Mhz PLL with Clock Injection Removal Setting2 2.5 — 2.7 — 3.1 ns 0.6 — 0.6 — 0.7 — ns ECP3-150EA 0.9 — 1.0 — 1.1 — n5 ECP3-150EA 1.5 — 1.6 — 1.8 — ns ECP3-150EA — 0.1 — 0.1 — 0.1 ns Stet ECP3-70E/95E — 2.2 — 2.3 — 2.5 ns Data 59“" ' P'0 "‘9‘“ Regis' ECP3-7UE/95E 0.6 — 0.7 — 0.8 — P'0 '"W‘ “995' gape-709951: 0.9 — 1.1 — 1.3 — Data Setup - PIO Input Regis- ECP3-70E/95E 1 G _ 1 9 _ 21 Delay ' ' ' Data Hotd - PIO Input Ftegrs- ECP3-7UE/95E 0 0 _ 0 0 _ put Data Delay ' ' -8 Description Device Min. ‘ Max. Mi Generic DDRX1 Inputs with Clock and Data (>10 Bits Wide) Centered at Fin (GDDR lock Input Left, Right and Top Sides & Clock Left, Right and Top Sides GDDH Data Setup Before CLK ECP3-150EA GDDR Data Hold After CLK ECP3-150EA fMAxﬁDDH DDRX1 Clock Frequency 5013345054 Generic DDFtX1 Inputs with Clock in the Center of Data Windo tsuepun Data Setup Before CLK E tHOGDDR Data Hold After CLK E fMijDDH DDRX1 Clock Frequency Generic DDRX1 Inputs with Clock and Data (> 10 B CLKIN Fin for Clock Input Data Left, Right and Tap Sides at Clock Left a tDVACLKGDDH Data Setup Before CLK tDVECLKGDDR Data Hold After fMAstDDH DDRX1 Clock Fr

3-17

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

fMAX_IO Clock Frequency of I/O and PFU Reg-

ister ECP3-70E/95E — 500 — 420 — 375 Mhz

General I/O Pin Parameters Using Dedicated Clock Input Primary Clock with PLL with Clock Injection Removal Setting2

tCOPLL Clock to Output - PIO Output Register ECP3-150EA —2.5 —2.7 —3.1 ns

tSUPLL Clock to Data Setup - PIO Input Regis-

ter ECP3-150EA 0.6 —0.6 —0.7 —ns

tHPLL Clock to Data Hold - PIO Input Regis-

ter ECP3-150EA 0.9 —1.0 —1.1 —ns

tSU_DELPLL Clock to Data Setup - PIO Input Regis-

ter with Data Input Delay ECP3-150EA 1.5 —1.6 —1.8 —ns

tH_DELPLL Clock to Data Hold - PIO Input Regis-

ter with Input Data Delay ECP3-150EA —0.1 —0.1 —0.1 ns

tCOPLL Clock to Output - PIO Output Register ECP3-70E/95E — 2.2 — 2.3 — 2.5 ns

tSUPLL Clock to Data Setup - PIO Input Regis-

ter ECP3-70E/95E 0.6 — 0.7 — 0.8 — ns

tHPLL Clock to Data Hold - PIO Input Regis-

ter ECP3-70E/95E 0.9 — 1.1 — 1.3 — ns

tSU_DELPLL Clock to Data Setup - PIO Input Regis-

ter with Data Input Delay ECP3-70E/95E 1.6 — 1.9 — 2.1 — ns

tH_DELPLL Clock to Data Hold - PIO Input Regis-

ter with Input Data Delay ECP3-70E/95E 0.0 — 0.0 — 0.0 — ns

Parameter Description Device

-8 -7 -6

UnitsMin. Max. Min. Max. Min. Max.

Generic DDR

Generic DDRX1 Inputs with Clock and Data (>10 Bits Wide) Centered at Pin (GDDRX1_RX.SCLK.Centered) Using PCLK

Pin for Clock Input

Data Left, Right and Top Sides & Clock Left, Right and Top Sides

tSUGDDR Data Setup Before CLK ECP3-150EA ———ps

tHGDDR Data Hold After CLK ECP3-150EA ———ps

fMAX_GDDR DDRX1 Clock Frequency ECP3-150EA ———MHz

Generic DDRX1 Inputs with Clock in the Center of Data Window, without DLL (GDDRX1_RX.ECLK.Centered)

tSUGDDR Data Setup Before CLK ECP3-70E/95E 515 — 515 — 515 — ps

tHOGDDR Data Hold After CLK ECP3-70E/95E 515 — 515 — 515 — ps

fMAX_GDDR DDRX1 Clock Frequency ECP3-70E/95E — 250 — 250 — 250 MHz

Generic DDRX1 Inputs with Clock and Data (> 10 Bits Wide) Aligned at Pin (GDDRX1_RX.SCLK.Aligned) using DLL-

CLKIN Pin for Clock Input

Data Left, Right and Top Sides & Clock Left and Right Sides

tDVACLKGDDR Data Setup Before CLK ECP3-150EA ———UI

tDVECLKGDDR Data Hold After CLK ECP3-150EA ———UI

fMAX_GDDR DDRX1 Clock Frequency ECP3-150EA ———MHz

Generic DDRX1 Inputs with Clock and Data Aligned, with DLL (GDDRX1_RX.ECLK.Aligned)

tDVACLKGDDR Data Setup Before CLK ECP3-70E/95E — 0.235 — 0.235 — 0.235 UI

tDVECLKGDDR Data Hold After CLK ECP3-70E/95E 0.765 — 0.765 — 0.765 — UI

LatticeECP3 External Switching Characteristics (Continued)1, 2

Over Recommended Commercial Operating Conditions

Parameter Description Device

-8 -7 -6

UnitsMin. Max. Min. Max. Min. Max.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

Max. Min. Max. Units 250 — 250 MHZ n (GDDRXLRXDOSCentered) Using DOS ns ns ECP3-150EA — — — ns Aligned at Pin (GDDRXLRXDOSAIigned) Using Dos Pin ECP3-150EA — — — Ul h‘ ECP3-150EA — — — Ul " 3"" ECP3-150EA — — — CLK (Top Side) ECP3-150EA — — After CLK (Top side) ECP3-150EA — — Clock Frequency (Top side) ECP3-150EA — — with Clock and Data (>10 Bits Wide) Centered at Fin (GDDRX27RX.ECL ides Data Setup Before CLK ECP3-150EA — Data Hold After CLK ECP3-150EA — fMijDDH DDRX2 Clock Frequency ECP3-150EA — Generic DDRXZ Inputs with Clock in the Center of Data Window, Without DL Data Setup Before CLK ECF'B-7OE/95E GDDH OGDDR Data Hold After CLK ECPaJOE/Q fMAxﬁGDDH DDR/DDRXZ Clock Frequencyg ECP3-7 Generic DDRXZ Inputs with Clock and Data (>10 Bits Wide) A Left and Right Side Using DLLCLKIN Pin for Clock lnpu Data Setup Before CLK (Left and ‘DVACLKGDDH Right Side) ‘ Data Hold After CLK (Left and Righ DVECLKGDDR Side) DDRX1 Clock Fre enc Le fMAstDDFi qu y ( Right Side) Top Side Using PCLK Pin tor Clock lnp ‘DVACLKGDDH Data Setup Beto t Data Hold After

3-18

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

fMAX_GDDR DDRX1 Clock Frequency ECP3-70E/95E — 250 — 250 — 250 MHz

Generic DDRX1 Inputs with Clock and Data (<10 Bits Wide) Centered at Pin (GDDRX1_RX.DQS.Centered) Using DQS

Pin for Clock Input

Left, Right and Top for Data and Clock

tSUGDDR Data Valid After CLK ECP3-150EA ———ns

tHGDDR Data Hold After CLK ECP3-150EA ———ns

fMAX_GDDR DDRX1 Clock Frequency ECP3-150EA ———ns

Generic DDRX1 Inputs with Clock and Data (<10 Bits Wide) Aligned at Pin (GDDRX1_RX.DQS.Aligned) Using DQS Pin

for Clock Input

Left and Right Sides

tDVACLKGDDR Data Setup Before CLK (Left and

Right Sides) ECP3-150EA ———UI

tDVECLKGDDR Data Hold After CLK (Left and Right

Sides) ECP3-150EA ———UI

fMAX_GDDR DDRX1 Clock Frequency (Left and

Right Sides) ECP3-150EA ———UI

Top Side

tDVACLKGDDR Data Setup Before CLK (Top Side) ECP3-150EA ———UI

tDVECLKGDDR Data Hold After CLK (Top Side) ECP3-150EA ———UI

fMAX_GDDR DDRX1 Clock Frequency (Top Side) ECP3-150EA ———UI

Generic DDRX2 Inputs with Clock and Data (>10 Bits Wide) Centered at Pin (GDDRX2_RX.ECLK.Centered) Using PCLK

Pin for Clock Input

Left and Right Sides

tSUGDDR Data Setup Before CLK ECP3-150EA ———ns

tHGDDR Data Hold After CLK ECP3-150EA ———ns

fMAX_GDDR DDRX2 Clock Frequency ECP3-150EA ———MHz

Generic DDRX2 Inputs with Clock in the Center of Data Window, Without DLL3 (GDDRX2_RX.ECLK.Centered)

tSUGDDR Data Setup Before CLK ECP3-70E/95E 260 — 312 — 352 — ps

tHOGDDR Data Hold After CLK ECP3-70E/95E 260 — 312 — 352 — ps

fMAX_GDDR DDR/DDRX2 Clock Frequency8ECP3-70E/95E — 500 — 420 — 375 MHz

Generic DDRX2 Inputs with Clock and Data (>10 Bits Wide) Aligned at Pin (GDDRX2_RX.ECLK.Aligned)

Left and Right Side Using DLLCLKIN Pin for Clock Input

tDVACLKGDDR Data Setup Before CLK (Left and

Right Side) ECP3-150EA ———UI

tDVECLKGDDR Data Hold After CLK (Left and Right

Side) ECP3-150EA ———UI

fMAX_GDDR DDRX1 Clock Frequency (Left and

Right Side) ECP3-150EA ———MHz

Top Side Using PCLK Pin for Clock Input

tDVACLKGDDR Data Setup Before CLK (Top Side) ECP3-150EA ———UI

tDVECLKGDDR Data Hold After CLK (Top Side) ECP3-150EA ———UI

fMAX_GDDR DDRX1 Clock Frequency (Top Side) ECP3-150EA ———MHz

Generic DDRX2 Inputs with Clock and Data Edges Aligned, with DLLDEL3 (GDDRX2_RX.ECLK.Aligned)

tDVACLKGDDR Data Valid After CLK ECP3-70E/95E — 0.235 — 0.235 — 0.235 UI

LatticeECP3 External Switching Characteristics (Continued)1, 2

Over Recommended Commercial Operating Conditions

Parameter Description Device

-8 -7 -6

UnitsMin. Max. Min. Max. Min. Max.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

Max. Min. Max. Units — 0.765 — Ul — 420 — 375 MHZ n (GDDRXLRXDOSCentered) using DOS — — ns ECP3-150EA — — n5 ECP3-150EA — — n5 Iigned at Pin (GDDRXZ ,RX.DOS.A|igned) Using DOS Pin ECP3-150EA — — — "d R'gl“ ECP3-150EA — — — ”Cy “‘9" 3"" ECF3-150EA — — — and Data (>10 Bits Wide) Centered at Pin (GDDRXLTX.SCLK.Cen d Belore CLK ECPS-lSOEA — Valid Aller CLK ECPS-l SOEA — RX1 Clock Frequency ECP3-150EA — — ,TX.ECLK.Centered) Outputs with clock in the center of data window, with PLL 90-degree sh Data lnvalid Before CLK ECP3-7DE/95E 670 — DR Data Invalid After CLK ECP3-7OE/95E 670 fMAxiGDDR DDRX1 Clock Frequency ECP3-7OE/95E Generic DDRX1 Output with Clock and Data (> 10 Bits , Right and Top Sides Wide) Aligned lDlBGDDFl Data Hold After CLK 50,234 tow/«Goon Data Setup Belore CLK Ecpgq lMAxﬁDDH DDRX1 Clock Frequency E Generic DDRX1 Outputs with clock and data edge align lDfEeDDH Data lnvalid Before CLK lDfAGDDR Data lnvalid After CLK lMAxﬁDDH DDRX1 Clock Frequency Generic DDRX1 Output with Clock and Left, Right and Top Sides lDVEGDDR Data Valfd Betor lDVAGDDH Data Valid Alter

3-19

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

tDVECLKGDDR Data Hold After CLK ECP3-70E/95E 0.765 — 0.765 — 0.765 — UI

fMAX_GDDR DDR/DDRX2 Clock Frequency8ECP3-70E/95E — 500 — 420 — 375 MHz

Generic DDRX2 Inputs with Clock and Data (<10 Bits Wide) Centered at Pin (GDDRX2_RX.DQS.Centered) using DQS

Pin for Clock Input

Left and Right Sides

tSUGDDR Data Setup Before CLK ECP3-150EA ———ns

tHGDDR Data Hold After CLK ECP3-150EA ———ns

fMAX_GDDR DDRX2 Clock Frequency ECP3-150EA ———ns

Generic DDRX2 Inputs with Clock and Data (<10 Bits Side) Aligned at Pin (GDDRX2_RX.DQS.Aligned) Using DQS Pin

for Clock Input

Left and Right Sides

tDVACLKGDDR Data Setup Before CLK (Left and

Right Side) ECP3-150EA ———

tDVECLKGDDR Data Hold After CLK (Left and Right

Side) ECP3-150EA ———

fMAX_GDDR DDRX2 Clock Frequency (Left and

Right Side) ECP3-150EA ———

Generic DDRX1 Output with Clock and Data (>10 Bits Wide) Centered at Pin (GDDRX1_TX.SCLK.Centered)

Left, Right and Top Sides

tDVBGDDR Data Valid Before CLK ECP3-150EA ———

tDVAGDDR Data Valid After CLK ECP3-150EA ———

fMAX_GDDR DDRX1 Clock Frequency ECP3-150EA ———

Generic DDRX1 Outputs with clock in the center of data window, with PLL 90-degree shifted clock ouput

(GDDRX1_TX.ECLK.Centered)

tDIBGDDR Data Invalid Before CLK ECP3-70E/95E 670 — 670 — 670 — ps

tDIAGDDR Data Invalid After CLK ECP3-70E/95E 670 — 670 — 670 — ps

fMAX_GDDR DDRX1 Clock Frequency ECP3-70E/95E — 250 — 250 — 250 MHz

Generic DDRX1 Output with Clock and Data (> 10 Bits Wide) Aligned at Pin (GDDRX1_TX.SCLK.Aligned)

Left, Right and Top Sides

tDIBGDDR Data Hold After CLK ECP3-150EA ———

tDIAGDDR Data Setup Before CLK ECP3-150EA ———

fMAX_GDDR DDRX1 Clock Frequency ECP3-150EA ———

Generic DDRX1 Outputs with clock and data edge aligned, without PLL

tDIBGDDR Data Invalid Before CLK ECP3-70E/95E — 330 — 330 — 330 ps

tDIAGDDR Data Invalid After CLK ECP3-70E/95E — 330 — 330 — 330 ps

fMAX_GDDR DDRX1 Clock Frequency ECP3-70E/95E — 250 — 250 — 250 MHz

Generic DDRX1 Output with Clock and Data (<10 Bits Wide) Centered at Pin (GDDRX1_TX.DQS.Centered)

Left, Right and Top Sides

tDVBGDDR Data Valid Before CLK ECP3-150EA ———

tDVAGDDR Data Valid After CLK ECP3-150EA ———

fMAX_GDDR DDRX1 Clock Frequency ECP3-150EA ———

LatticeECP3 External Switching Characteristics (Continued)1, 2

Over Recommended Commercial Operating Conditions

Parameter Description Device

-8 -7 -6

UnitsMin. Max. Min. Max. Min. Max.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

Max. Min. l Max. Units ,TX.ECLK.AIigned) _ _ p5 _ _ _ p5 — — — MHz Without PLL 90-degree shifted clock output5 ECP3-70E/95E — 200 — 225 — 250 p5 ECP3-7OE/95E — 200 — 225 — 250 p5 ECP3-70E/95E — 500 — 420 — 375 MHZ Wide) Centered at Pin Using DOSDLL (GDDRX27TX.DGS- ECP3-150EA — — — ECPS-lSOEA — — — ncy ECP3-150EA — — — and Data (> 10 Bits Wide) Centered at Pin Using PLL (GDDRXZJXPLL d Belore CLK ECPS-lSOEA — — Valid Aller CLK ECPS—l SOEA — RXZ Clock Frequency ECP3-150EA — — Outputs with Clock Edge in the Cente ,TX.FLL.Centered) r at Data Window, with Data Valld Beiore CLK ECP3-7DE/95E 300 Data Valid Ailey CLK ECP3-7OE/95E 300 lMAxieDDFt DDR/DDRX2 Clock Frequencyg ECP3-7OE/95E Parameter Description Device Memory Interlace DDFtIDDFtZ SDFtAM IIO Pin Parameters (Input Data are tmm Data Valid Alter Dos (DDR Read) E tDVEDQ Data Hold After DOS (DDFt Read) loaves Data Valid Before DQS lDQVAS Data Valid Aﬂer DQS tMijDH DDR Clock Frequency lMijDHz DDR2 clock irequency tDVADQ Data Valld Aitev lDVEDQ Data Hold After

3-20

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

Generic DDRX2 Output with Clock and Data (> 10 Bits Wide) Aligned at Pin (GDDRX2_TX.ECLK.Aligned)

Left and Right Sides

tDIBGDDR Data Setup Before CLK ECP3-150EA ———ps

tDIAGDDR Data Hold After CLK ECP3-150EA ———ps

fMAX_GDDR DDRX2 Clock Frequency ECP3-150EA ———MHz

Generic DDRX2 Outputs with Clock and Data Edges Aligned, Without PLL 90-degree shifted clock output5

(GDDRX2_TX.Aligned)

tDIBGDDR Data Invalid Before Clock ECP3-70E/95E — 200 — 225 — 250 ps

tDIAGDDR Data Invalid After Clock ECP3-70E/95E — 200 — 225 — 250 ps

fMAX_GDDR DDR/DDRX2 Clock Frequency8ECP3-70E/95E — 500 — 420 — 375 MHz

Generic DDRX2 Output with Clock and Data (> 10 Bits Wide) Centered at Pin Using DQSDLL (GDDRX2_TX.DQS-

DLL.Centered)

Left and Right Sides

tDVBGDDR Data Valid Before CLK ECP3-150EA ———ns

tDVAGDDR Data Valid After CLK ECP3-150EA ———ns

fMAX_GDDR DDRX2 Clock Frequency ECP3-150EA ———ns

Generic DDRX2 Output with Clock and Data (> 10 Bits Wide) Centered at Pin Using PLL (GDDRX2_TX.PLL.Centered)

Left and Right Sides

tDVBGDDR Data Valid Before CLK ECP3-150EA ———ns

tDVAGDDR Data Valid After CLK ECP3-150EA ———ns

fMAX_GDDR DDRX2 Clock Frequency ECP3-150EA ———ns

Generic DDRX2 Outputs with Clock Edge in the Center of Data Window, with PLL 90-degree Shifted Clock Output6

(GDDRX2_TX.PLL.Centered)

tDVBGDDR Data Valid Before CLK ECP3-70E/95E 300 — 370 — 417 — ps

tDVAGDDR Data Valid After CLK ECP3-70E/95E 300 — 370 — 417 — ps

fMAX_GDDR DDR/DDRX2 Clock Frequency8ECP3-70E/95E — 500 — 420 — 375 MHz

Parameter Description Device

-8 -7 -6

UnitsMin. Max. Min. Max. Min. Max.

Memory Interface

DDR/DDR2 SDRAM I/O Pin Parameters (Input Data are Strobe Edge Aligned, Output Strobe Edge is Data Centered)4

tDVADQ Data Valid After DQS (DDR Read) ECP3-150EA —0.225 —0.225 —0.225 UI

tDVEDQ Data Hold After DQS (DDR Read) ECP3-150EA 0.64 —0.64 —0.64 —UI

tDQVBS Data Valid Before DQS ECP3-150EA 0.25 —0.25 —0.25 —UI

tDQVAS Data Valid After DQS ECP3-150EA 0.25 —0.25 —0.25 —UI

fMAX_DDR DDR Clock Frequency ECP3-150EA 95 200 95 200 95 166 MHz

fMAX_DDR2 DDR2 clock frequency ECP3-150EA 133 266 133 200 133 166 MHz

tDVADQ Data Valid After DQS (DDR Read) ECP3-70E/95E — 0.225 — 0.225 — 0.225 UI

tDVEDQ Data Hold After DQS (DDR Read) ECP3-70E/95E 0.64 — 0.64 — 0.64 — UI

tDQVBS Data Valid Before DQS ECP3-70E/95E 0.25 — 0.25 — 0.25 — UI

tDQVAS Data Valid After DQS ECP3-70E/95E 0.25 — 0.25 — 0.25 — UI

fMAX_DDR DDR Clock Frequency ECP3-70E/95E 95 200 95 200 95 133 MHz

LatticeECP3 External Switching Characteristics (Continued)1, 2

Over Recommended Commercial Operating Conditions

Parameter Description Device

-8 -7 -6

UnitsMin. Max. Min. Max. Min. Max.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

Max. Min. Max. Units 200 133 166 MHZ 0.225 — 0.225 — 0.225 Ul 0.64 — 0.64 — 0.64 — Ul 0.25 — 0.25 — 0.25 — Ul 0.25 — 0.25 — 0.25 — Ul ECP3-150EA 266 400 266 333 266 300 MHZ \y stawer and can be extracted tram the IspLEvER sottware based an SSTLIE x skew numbers. tms wm be supported m a luture release ase canmtmns, System panormance may vary upan the user envlmnment

3-21

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

fMAX_DDR2 DDR2 Clock Frequency ECP3-70E/95E 133 266 133 200 133 166 MHz

DDR3 (Using PLL for SCLK) I/O Pin Parameters

tDVADQ Data Valid After DQS (DDR Read) ECP3-150EA —0.225 —0.225 —0.225 UI

tDVEDQ Data Hold After DQS (DDR Read) ECP3-150EA 0.64 —0.64 —0.64 —UI

tDQVBS Data Valid Before DQS ECP3-150EA 0.25 —0.25 —0.25 —UI

tDQVAS Data Valid After DQS ECP3-150EA 0.25 —0.25 —0.25 —UI

fMAX_DDR3 DDR3 clock frequency ECP3-150EA 266 400 266 333 266 300 MHz

1. Commercial timing numbers are shown. Industrial numbers are typically slower and can be extracted from the ispLEVER software.

2. General I/O timing numbers based on LVCMOS 2.5, 12mA, 0pf load.

3. Generic DDR timing numbers based on LVDS I/O.

4. DDR timing numbers based on SSTL25. DDR2 timing numbers based on SSTL18.

5. DDR3 timing numbers based on SSTL15.

6. Uses LVDS I/O standard.

7. The current version of software does not support per bank skew numbers; this will be supported in a future release.

8. Maximum clock frequencies are tested under best case conditions. System performance may vary upon the user environment.

LatticeECP3 External Switching Characteristics (Continued)1, 2

Over Recommended Commercial Operating Conditions

Parameter Description Device

-8 -7 -6

UnitsMin. Max. Min. Max. Min. Max.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

—nn— —nn— | || II III II III II >§8882< w="" iii="" ii="" —="">ll‘——n'n—

3-22

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

Figure 3-6. Generic DDR/DDR2 (With Clock and Data Edges Aligned)

CLK

RDTCLK

Data (RDAT, RCTL)

Data (TDAT, TCTL)

DIBGDDR

DVACLKGDDRDVACLKGDDR

DVECLKGDDR DVECLKGDDR

DIAGDDR

Transmit Parameters

Receive Parameters

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

ameters /DDRZ Parameters (With Clock Center on Data Window) Transmlt Parameters c I I I : I I I W W . W . W I I I t IH: I : 4—D: momma I‘ I I‘ .' IWCKGDDR ‘uvAcKeuua tnI/Izchm Receive . i . c LOCK I )l I I \ / \ | | I I I I : I I SUGDDR I I Mam

3-23

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

Figure 3-7. DDR/DDR2/DDR3 SDRAM

Figure 3-8. Generic DDR/DDR2 Parameters (With Clock Center on Data Window)

Transmit Parameters

DQS

Receive Parameters

tDQVBS

tDVADQ

tDVEDQ tDVEDQ

tDVADQ

tDQVAS

tDQVAS tDQVBS

DVBCKGDDR DVACKGDDR

HGDDR

SUGDDR

DVACKGDDR DVBCKGDDR

Transmit Parameters

CLOCK

DATA

Receive Parameters

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

x. Min. Max. Units. — 0.163 — 0.179 n5 — 0.307 — 0.342 n5 3 — 0.674 — 0.756 n5 .298 — 0.345 — 0.391 ns — 0.144 — 0.153 — n5 -0.097 — -0.103 — -0.109 — r15 0.061 — 0.068 — 0.075 — n5 0.019 — 0.013 — 0.015 — n5 — 0.243 — 0.273 — 0.303 ns — 0.710 — 0.803 — 0.897 -0.137 — -0.155 — -0.174 — 0.188 — 0.217 — 0.246 — -0.227 — -0.257 — -0.286 me 0.240 — 0.275 — 0.310 Enable Setup Tlme -0.055 — -0.055 — -0.063 Read Enable Hold Tlme 0.059 — 0.059 — PIO lnputloutput Butler Timing Input Butler Delay (LVCMOSZS) — 0.423 — Output Butler Delay (chmoszs) — 1.115 — GIC lnputloutput Timing 310 lagggteglster Setup Tlme (Data Belpre 0.956 LP‘O Input Register Hold Time (Data after Clock) 0.313 tcooiplo Output Register Clock to Output Delay‘ tSUCEiplo Input Register Clock Enable Setup Time 0 ‘HCEiplO Input Register Clock Enable Hold Time ‘SULSFLF'lO Set/Reset Setup Time IHLSFLP‘O Set/Reset Hold Time EBR Timing ‘coiaR Clock (Head) to output from Ad Clock (Write) to output lr hogan ister ‘SUDATAiEBFl Setup Data to EBR ‘HDATAjBR Hold Data to EBR

3-24

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

LatticeECP3 Internal Switching Characteristics1, 2

Over Recommended Commercial Operating Conditions

Parameter Description

-8 -7 -6

Units.Min. Max. Min. Max. Min. Max.

PFU/PFF Logic Mode Timing

tLUT4_PFU LUT4 delay (A to D inputs to F output) — 0.147 — 0.163 — 0.179 ns

tLUT6_PFU LUT6 delay (A to D inputs to OFX output) — 0.273 — 0.307 — 0.342 ns

tLSR_PFU Set/Reset to output of PFU (Asynchronus) — 0.593 — 0.674 — 0.756 ns

tLSRREC_PFU Asynchronous Set/Reset recovery time for

PFU Logic —0.298—0.345—0.391ns

tSUM_PFU Clock to Mux (M0,M1) Input Setup Time 0.134 — 0.144 — 0.153 — ns

tHM_PFU Clock to Mux (M0,M1) Input Hold Time -0.097 — -0.103 — -0.109 — ns

tSUD_PFU Clock to D input setup time 0.061 — 0.068 — 0.075 — ns

tHD_PFU Clock to D input hold time 0.019 — 0.013 — 0.015 — ns

tCK2Q_PFU Clock to Q delay, (D-type Register 

Configuration) —0.243—0.273—0.303ns

PFU Dual Port Memory Mode Timing

tCORAM_PFU Clock to Output (F Port) — 0.710 — 0.803 — 0.897 ns

tSUDATA_PFU Data Setup Time -0.137 — -0.155 — -0.174 — ns

tHDATA_PFU Data Hold Time 0.188 — 0.217 — 0.246 — ns

tSUADDR_PFU Address Setup Time -0.227 — -0.257 — -0.286 — ns

tHADDR_PFU Address Hold Time 0.240 — 0.275 — 0.310 — ns

tSUWREN_PFU Write/Read Enable Setup Time -0.055 — -0.055 — -0.063 — ns

tHWREN_PFU Write/Read Enable Hold Time 0.059 — 0.059 — 0.071 — ns

PIC Timing

PIO Input/Output Buffer Timing

tIN_PIO Input Buffer Delay (LVCMOS25) — 0.423 — 0.466 — 0.508 ns

tOUT_PIO Output Buffer Delay (LVCMOS25) — 1.115 — 1.155 — 1.196 ns

IOLOGIC Input/Output Timing

tSUI_PIO Input Register Setup Time (Data Before

Clock) 0.956 — 1.124 — 1.293 — ns

tHI_PIO Input Register Hold Time (Data after Clock) 0.313 — 0.395 — 0.378 — ns

tCOO_PIO Output Register Clock to Output Delay4—1.455—1.564—1.674ns

tSUCE_PIO Input Register Clock Enable Setup Time 0.220 — 0.185 — 0.150 — ns

tHCE_PIO Input Register Clock Enable Hold Time -0.085 — -0.072 — -0.058 — ns

tSULSR_PIO Set/Reset Setup Time 0.117 — 0.103 — 0.088 — ns

tHLSR_PIO Set/Reset Hold Time -0.107 — -0.094 — -0.081 — ns

EBR Timing

tCO_EBR Clock (Read) to output from Address or Data — 2.78 — 2.89 — 2.99 ns

tCOO_EBR Clock (Write) to output from EBR output Reg-

ister — 0.31 — 0.32 — 0.33 ns

tSUDATA_EBR Setup Data to EBR Memory -0.218 — -0.227 — -0.237 — ns

tHDATA_EBR Hold Data to EBR Memory 0.249 — 0.257 — 0.265 — ns

tSUADDR_EBR Setup Address to EBR Memroy -0.071 — -0.070 — -0.068 — ns

tHADDR_EBR Hold Address to EBR Memory 0.118 — 0.098 — 0.077 — ns

tSUWREN_EBR Setup Write/Read Enable to PFU Memory -0.107 — -0.106 — -0.106 — ns

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

P Register Hold Time x. Min. Max. Units. 0.149 — ns 0.096 0.104 n5 -0.080 -0.094 ns -0.070 -0.068 ms .118 0.098 0.077 ns 0.32 — 0.36 — 0.39 — ns 0.17 — -0.19 — -0.21 — ns 2.23 — 2.30 — 2.37 — ns -1.02 — -1.09 — -1.15 — 3.09 — 3.22 — 3.34 — -1.67 — -1.76 — -1.84 — Ouipui Time — 3.68 — 4.03 — 4. Clock lo Ouipul Time — 1.30 — 1.47 — er Clock lo Output Time — 0.58 — 0.60 — egisiev Seiup Time 0.31 — 0.35 — Regisier Hold Time -0.20 — -0.24 — scadeidaia ihrough ALU lo Outpui Regisier Seiup Time 1'55 _ 1'67 Cascadeidata through ALU lo Ouipul 4144 _ _0-5 parameiers are characterized but n01 tested on every demce. mmercrai umrng numbers are shown, indusmai ilmmg numbers are Iypicaily slower an P slice rs conﬁgured m Muiliply Add/Sub 13x15 made. The 00mm register Is In Flipriiop mode.

3-25

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

tHWREN_EBR Hold Write/Read Enable to PFU Memory 0.141 — 0.145 — 0.149 — ns

tSUCE_EBR Clock Enable Setup Time to EBR Output

tHCE_EBR Clock Enable Hold Time to EBR Output

tSUBE_EBR Byte Enable Set-Up Time to EBR Output

tHBE_EBR Byte Enable Hold Time to EBR Output

DSP Block Timing3

tSUI_DSP Input Register Setup Time 0.32 — 0.36 — 0.39 — ns

tHI_DSP Input Register Hold Time -0.17 — -0.19 — -0.21 — ns

tSUP_DSP Pipeline Register Setup Time 2.23 — 2.30 — 2.37 — ns

tHP_DSP Pipeline Register Hold Time -1.02 — -1.09 — -1.15 — ns

tSUO_DSP Output Register Setup Time 3.09 — 3.22 — 3.34 — ns

tHO_DSP Output Register Hold Time -1.67 — -1.76 — -1.84 — ns

tCOI_DSP Input Register Clock to Output Time — 3.68 — 4.03 — 4.38 ns

tCOP_DSP Pipeline Register Clock to Output Time — 1.30 — 1.47 — 1.64 ns

tCOO_DSP Output Register Clock to Output Time — 0.58 — 0.60 — 0.62 ns

tSUOPT_DSP Opcode Register Setup Time 0.31 — 0.35 — 0.39 — ns

tHOPT_DSP Opcode Register Hold Time -0.20 — -0.24 — -0.27 — ns

tSUDATA_DSP Cascade_data through ALU to Output

tHPDATA_DSP Cascade_data through ALU to Output

1. Internal parameters are characterized but not tested on every device.

2. Commercial timing numbers are shown. Industrial timing numbers are typically slower and can be extracted from the ispLEVER software.

3. DSP slice is configured in Multiply Add/Sub 18x18 mode.

4. The output register is in Flip-flop mode.

LatticeECP3 Internal Switching Characteristics1, 2 (Continued)

Over Recommended Commercial Operating Conditions

Parameter Description

-8 -7 -6

Units.Min. Max. Min. Max. Min. Max.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

XXXXXXXXXXXX HXXXX‘XHH n‘ XXX eglstered a: me pasmve edge oX me dock and ompm data appears aﬂer me pasmve a 19 Made with Input and Output Registers /\/\X\/\/\/\ XXX XXX XXX XXX XXX XXX XXX

3-26

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

Timing Diagrams

Figure 3-9. Read/Write Mode (Normal)

Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock.

Figure 3-10. Read/Write Mode with Input and Output Registers

A0 A1 A0 A1

D0 D1

DOA

CO_EBR

D0 D1 D0

DIA

ADA

WEA

CSA

CLKA

A0 A1 A0 A0

D0 D1

output is only updated during a read cycle

D0 D1

Mem(n) data from previous read

DIA

ADA

WEA

CSA

CLKA

DOA (Regs)

tSU tH

tCOO_EBR tCOO_EBR

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

l .\ X41.» M W, x x W x SW“ :1 a: me pasmve edge oﬂhe dock and output data appears aner me posmve edge or

3-27

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

Figure 3-11. Write Through (SP Read/Write on Port A, Input Registers Only)

Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock.

A0 A1 A0

D0 D1

tSU

tACCESS tACCESS tACCESS

D2 D3 D4

D0 D1 D2

Data from Prev Read

or Write

Three consecutive writes to A0

DOA

DIA

ADA

WEA

CSA

CLKA

tACCESS

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

0.03 -0.01 -0.03 ns 0.03 0.00 -0.04 ns 0.03 0.00 -0.04 ns 0.03 0.00 -0.04 ns 0.03 0.00 -0.03 ns 0.03 -0.01 -0.03 ns 0.03 0.00 -0.04 ns 0.03 -0.01 -0.03 ns 0.17 0.07 -0.04 ns 1 8V 0.20 0.17 0.13 ns IO:1 8V 0.20 0.17 0.13 ns ssI 0.20 0.17 0.13 ns class II 0.20 0.17 0.13 I,VCCIO:15V 0.10 0.12 0.13 HSTL15 classl 0.10 0.12 0. ass I, VCCIO : 3 0V 0.17 0.23 0. class II, VCCIO : 3 0V 0.17 0.23 Dilleremial SSTLj class I 0.17 0.23 Diﬂerential SSTLJ class II 0.17 SSTL72 class I, VCCIO : 2.5V 0.12 SSTL72 class II, VCCIO : .5V Dilleremial SSTL72 class I Dill Diﬂerential SSTL72 class II SSTL718 class I, VCCIO : 1.8V SSTL187II SSTL718 class II, VCCIO : 1.8V SSTL18DJ Diﬂeremial SSTLJB class I SSTL18D7II Dineremial SSTLJ 8 class II SSTL15 SSTLJ 5, VCCIO : 1.5V SSTL15D DiIIerentiaI SSTLJS LVTTL33 LVTTL, VCCIO : 3.0V LVCMOSSS LVCMOS, VCCIO : 3.0V LVCMOS25 LVCMOS, VCCIO : 2.5V LVCMOS18 LVCMOS, VCCIO : 1.8V LVCMOS15 LVCMOS, VCCIO : LVCMOS12 LVCMOS, VC PCI33 PCI, VCCIO : Oulpul Adjusters LVDS25E LVDS, E

3-28

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

LatticeECP3 Family Timing Adders1, 2, 3, 4, 5

Over Recommended Commercial Operating Conditions

Buffer Type Description -8 -7 -6 Units

Input Adjusters

LVDS25E LVDS, Emulated, VCCIO = 2.5V 0.03 -0.01 -0.03 ns

LVDS25 LVDS, VCCIO = 2.5V 0.03 0.00 -0.04 ns

BLVDS25 BLVDS, Emulated, VCCIO = 2.5V 0.03 0.00 -0.04 ns

MLVDS25 MLVDS, Emulated, VCCIO = 2.5V 0.03 0.00 -0.04 ns

RSDS25 RSDS, VCCIO = 2.5V 0.03 0.00 -0.03 ns

PPLVDS Point-to-Point LVDS 0.03 -0.01 -0.03 ns

TRLVDS Transition-Reduced LVDS 0.03 0.00 -0.04 ns

Mini MLVDS Mini LVDS 0.03 -0.01 -0.03 ns

LVPECL33 LVPECL, Emulated, VCCIO = 3.0V 0.17 0.07 -0.04 ns

HSTL18_I HSTL_18 class I, VCCIO = 1.8V 0.20 0.17 0.13 ns

HSTL18_II HSTL_18 class II, VCCIO = 1.8V 0.20 0.17 0.13 ns

HSTL18D_I Differential HSTL 18 class I 0.20 0.17 0.13 ns

HSTL18D_II Differential HSTL 18 class II 0.20 0.17 0.13 ns

HSTL15_I HSTL_15 class I, VCCIO = 1.5V 0.10 0.12 0.13 ns

HSTL15D_I Differential HSTL 15 class I 0.10 0.12 0.13 ns

SSTL33_I SSTL_3 class I, VCCIO = 3.0V 0.17 0.23 0.28 ns

SSTL33_II SSTL_3 class II, VCCIO = 3.0V 0.17 0.23 0.28 ns

SSTL33D_I Differential SSTL_3 class I 0.17 0.23 0.28 ns

SSTL33D_II Differential SSTL_3 class II 0.17 0.23 0.28 ns

SSTL25_I SSTL_2 class I, VCCIO = 2.5V 0.12 0.14 0.16 ns

SSTL25_II SSTL_2 class II, VCCIO = 2.5V 0.12 0.14 0.16 ns

SSTL25D_I Differential SSTL_2 class I 0.12 0.14 0.16 ns

SSTL25D_II Differential SSTL_2 class II 0.12 0.14 0.16 ns

SSTL18_I SSTL_18 class I, VCCIO = 1.8V 0.08 0.06 0.04 ns

SSTL18_II SSTL_18 class II, VCCIO = 1.8V 0.08 0.06 0.04 ns

SSTL18D_I Differential SSTL_18 class I 0.08 0.06 0.04 ns

SSTL18D_II Differential SSTL_18 class II 0.08 0.06 0.04 ns

SSTL15 SSTL_15, VCCIO = 1.5V 0.087 0.059 0.032 ns

SSTL15D Differential SSTL_15 0.087 0.025 -0.036 ns

LVTTL33 LVTTL, VCCIO = 3.0V 0.05 0.05 0.05 ns

LVCMOS33 LVCMOS, VCCIO = 3.0V 0.05 0.05 0.05 ns

LVCMOS25 LVCMOS, VCCIO = 2.5V 0.00 0.00 0.00 ns

LVCMOS18 LVCMOS, VCCIO = 1.8V 0.06 0.08 0.11 ns

LVCMOS15 LVCMOS, VCCIO = 1.5V 0.17 0.21 0.25 ns

LVCMOS12 LVCMOS, VCCIO = 1.2V 0.01 0.05 0.08 ns

PCI33 PCI, VCCIO = 3.0V 0.05 0.05 0.05 ns

Output Adjusters

LVDS25E LVDS, Emulated, VCCIO = 2.5V 0.15 0.15 0.16 ns

LVDS25 LVDS, VCCIO = 2.5V 0.02 0.08 0.13 ns

BLVDS25 BLVDS, Emulated, VCCIO = 2.5V 0.00 -0.02 -0.04 ns

MLVDS25 MLVDS, Emulated, VCCIO = 2.5V 0.00 -0.01 -0.03 ns

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

0.05 0.10 0.16 ns -0.10 -0.05 0.01 ns -0.02 -0.04 -0.06 ns -0.19 -0.16 -0.12 ns -0.30 -0.28 -0.25 ns -0.19 -0.16 -0.12 ns -0.30 -0.28 -0.25 ns -0.22 -0.19 -0.16 ns ive -0.22 -0.19 -0.16 ns 0.08 0.13 0.19 ns -0.20 -0.17 -0.14 ns ass i 0.08 0.13 0.18 ns ass ii -0.20 -0.17 -0.14 ns 8mA drive, VCCID : 2.5V -0.06 -0.02 0.02 assll16mA drive, VCCiO : 2.5V -0.19 -0.15 -0.12 SSTL72 class i BmA drive -0.06 -0.02 0. |SSTL72 Class H 16mA drive -0.19 -0.15 -0 8 class I, VCCIO 21.8V -0.14 -0.10 SSTLJ .8 class II 8mA drive, VCCiD : 1.8V -0.20 -0.17 Diiierential SSTLJ ,8 class i -0.14 Diiierential SSTLJ 8 class ii BmA drive -0.20 SSTLJ .5, VCCIO : 1.5V Diiiereniial SSTLJ 5 mA LVTTL AmA drive, VCCIO : 3.0V mA LVTTL 8mA drive, VCCIO : 3.0V LVTTL33712mA LVTTL 12mA drive, VCCIO : 3.0V LVTTL33716mA LVTTL16mA drive, VCCI — 3.0V LVTTL33720mA LVTTL 20mA drive, VCCIO : 3.0V LVCMOSSSJimA LVCMOS 3.3 AmA drive, fast siew rate LVCM083378mA LVCMOS 3.3 8mA drive, fasi siew rate LVCMOSSSJZmA LVCMOS 3.312mA drive, fasi s LVCMOSSSJ6mA LVCMOS 3.316mA drive, fasi s LVCM0833720mA LVCMOS 3.3 20mA drive, LVCMOSZSJimA LVCMOS 2.5 4mA drive, fa LVCM082578mA LVCMOS 2.5 8mA d LVCMOSZSJZmA LVCMOS 2.512mA LVCM0825716mA LVCMOS 2.5 LVCM0825720mA LVCMO LVCMOS1874mA LVCMO

3-29

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

RSDS25 RSDS, VCCIO = 2.5V 0.05 0.10 0.16 ns

PPLVDS Point-to-Point LVDS, Emulated, VCCIO = 2.5V -0.10 -0.05 0.01 ns

LVPECL33 LVPECL, Emulated, VCCIO = 3.0V -0.02 -0.04 -0.06 ns

HSTL18_I HSTL_18 class I 8mA drive, VCCIO = 1.8V -0.19 -0.16 -0.12 ns

HSTL18_II HSTL_18 class II, VCCIO = 1.8V -0.30 -0.28 -0.25 ns

HSTL18D_I Differential HSTL 18 class I 8mA drive -0.19 -0.16 -0.12 ns

HSTL18D_II Differential HSTL 18 class II -0.30 -0.28 -0.25 ns

HSTL15_I HSTL_15 class I 4mA drive, VCCIO = 1.5V -0.22 -0.19 -0.16 ns

HSTL15D_I Differential HSTL 15 class I 4mA drive -0.22 -0.19 -0.16 ns

SSTL33_I SSTL_3 class I, VCCIO = 3.0V 0.08 0.13 0.19 ns

SSTL33_II SSTL_3 class II, VCCIO = 3.0V -0.20 -0.17 -0.14 ns

SSTL33D_I Differential SSTL_3 class I 0.08 0.13 0.18 ns

SSTL33D_II Differential SSTL_3 class II -0.20 -0.17 -0.14 ns

SSTL25_I SSTL_2 class I 8mA drive, VCCIO = 2.5V -0.06 -0.02 0.02 ns

SSTL25_II SSTL_2 class II 16mA drive, VCCIO = 2.5V -0.19 -0.15 -0.12 ns

SSTL25D_I Differential SSTL_2 class I 8mA drive -0.06 -0.02 0.02 ns

SSTL25D_II Differential SSTL_2 class II 16mA drive -0.19 -0.15 -0.12 ns

SSTL18_I SSTL_1.8 class I, VCCIO = 1.8V -0.14 -0.10 -0.07 ns

SSTL18_II SSTL_1.8 class II 8mA drive, VCCIO = 1.8V -0.20 -0.17 -0.14 ns

SSTL18D_I Differential SSTL_1.8 class I -0.14 -0.10 -0.07 ns

SSTL18D_II Differential SSTL_1.8 class II 8mA drive -0.20 -0.17 -0.14 ns

SSTL15 SSTL_1.5, VCCIO = 1.5V 0.07 0.08 0.08 ns

SSTL15D Differential SSTL_15 0.07 0.08 0.08 ns

LVTTL33_4mA LVTTL 4mA drive, VCCIO = 3.0V 0.21 0.23 0.25 ns

LVTTL33_8mA LVTTL 8mA drive, VCCIO = 3.0V 0.09 0.09 0.10 ns

LVTTL33_12mA LVTTL 12mA drive, VCCIO = 3.0V 0.02 0.03 0.03 ns

LVTTL33_16mA LVTTL 16mA drive, VCCIO = 3.0V 0.12 0.13 0.13 ns

LVTTL33_20mA LVTTL 20mA drive, VCCIO = 3.0V 0.08 0.08 0.09 ns

LVCMOS33_4mA LVCMOS 3.3 4mA drive, fast slew rate 0.21 0.23 0.25 ns

LVCMOS33_8mA LVCMOS 3.3 8mA drive, fast slew rate 0.09 0.09 0.10 ns

LVCMOS33_12mA LVCMOS 3.3 12mA drive, fast slew rate 0.02 0.03 0.03 ns

LVCMOS33_16mA LVCMOS 3.3 16mA drive, fast slew rate 0.12 0.13 0.13 ns

LVCMOS33_20mA LVCMOS 3.3 20mA drive, fast slew rate 0.08 0.08 0.09 ns

LVCMOS25_4mA LVCMOS 2.5 4mA drive, fast slew rate 0.12 0.12 0.12 ns

LVCMOS25_8mA LVCMOS 2.5 8mA drive, fast slew rate 0.05 0.05 0.05 ns

LVCMOS25_12mA LVCMOS 2.5 12mA drive, fast slew rate 0.00 0.00 0.00 ns

LVCMOS25_16mA LVCMOS 2.5 16mA drive, fast slew rate 0.08 0.08 0.08 ns

LVCMOS25_20mA LVCMOS 2.5 20mA drive, fast slew rate 0.04 0.04 0.04 ns

LVCMOS18_4mA LVCMOS 1.8 4mA drive, fast slew rate 0.08 0.09 0.09 ns

LVCMOS18_8mA LVCMOS 1.8 8mA drive, fast slew rate 0.02 0.01 0.01 ns

LVCMOS18_12mA LVCMOS 1.8 12mA drive, fast slew rate -0.03 -0.03 -0.03 ns

LVCMOS18_16mA LVCMOS 1.8 16mA drive, fast slew rate 0.03 0.03 0.03 ns

LatticeECP3 Family Timing Adders1, 2, 3, 4, 5 (Continued)

Over Recommended Commercial Operating Conditions

Buffer Type Description -8 -7 -6 Units

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

0.09 0.10 0.10 ns 0.01 0.01 0.00 ns 0.08 0.08 0.08 ns -0.02 -0.02 -0.02 ns 1.64 1.71 1.77 ns 1.39 1.45 1.51 ns 1.21 1.27 1.33 ns 1.43 1.49 1.55 ns slew vale 1.23 1.28 1.34 ns vale 1.66 1.70 1.74 ns slew vale 1.39 1.43 1.46 ns slow slew rate 1.20 1.24 1.28 ns slow slew rale 1.42 1.45 1.49 ns drive, slow slew vale 1.22 1.26 1.29 4mA drive. slow slew vale 1.61 1.65 1.68 8mA drive. slow slew rale 1.32 1.36 1. .812mA drive, slow slew vale 1.14 1.17 1. LVCMOS1.816mA drive, slow slew rate 1.35 1.38 LVCMOS 1.5 4mA drive, slow slew rate 1.57 1.60 LVCMOS 1.5 SmA drive. slow slew rale 0.01 LVCMOS 1.2 2mA drive. slow slew vale 1.51 LVCMOS1.2 emA drive, slow slew rale F'Cl, VCCIO : 3.0V aers are characlenzed bul nol lesled on every device. llmmg measured wrm lhe load specrl‘rea m Swllchmg Tesl Cenamon lame. omer slandards lesled accommg to me appropriale specmcatlons. all l/O standards and drive slrengths are supported lor all banks See me Arcmleemr mmereral um‘rng numbers are shown, lndusmal numbers are typically slower an

3-30

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

LVCMOS15_4mA LVCMOS 1.5 4mA drive, fast slew rate 0.09 0.10 0.10 ns

LVCMOS15_8mA LVCMOS 1.5 8mA drive, fast slew rate 0.01 0.01 0.00 ns

LVCMOS12_2mA LVCMOS 1.2 2mA drive, fast slew rate 0.08 0.08 0.08 ns

LVCMOS12_6mA LVCMOS 1.2 6mA drive, fast slew rate -0.02 -0.02 -0.02 ns

LVCMOS33_4mA LVCMOS 3.3 4mA drive, slow slew rate 1.64 1.71 1.77 ns

LVCMOS33_8mA LVCMOS 3.3 8mA drive, slow slew rate 1.39 1.45 1.51 ns

LVCMOS33_12mA LVCMOS 3.3 12mA drive, slow slew rate 1.21 1.27 1.33 ns

LVCMOS33_16mA LVCMOS 3.3 16mA drive, slow slew rate 1.43 1.49 1.55 ns

LVCMOS33_20mA LVCMOS 3.3 20mA drive, slow slew rate 1.23 1.28 1.34 ns

LVCMOS25_4mA LVCMOS 2.5 4mA drive, slow slew rate 1.66 1.70 1.74 ns

LVCMOS25_8mA LVCMOS 2.5 8mA drive, slow slew rate 1.39 1.43 1.46 ns

LVCMOS25_12mA LVCMOS 2.5 12mA drive, slow slew rate 1.20 1.24 1.28 ns

LVCMOS25_16mA LVCMOS 2.5 16mA drive, slow slew rate 1.42 1.45 1.49 ns

LVCMOS25_20mA LVCMOS 2.5 20mA drive, slow slew rate 1.22 1.26 1.29 ns

LVCMOS18_4mA LVCMOS 1.8 4mA drive, slow slew rate 1.61 1.65 1.68 ns

LVCMOS18_8mA LVCMOS 1.8 8mA drive, slow slew rate 1.32 1.36 1.39 ns

LVCMOS18_12mA LVCMOS 1.8 12mA drive, slow slew rate 1.14 1.17 1.21 ns

LVCMOS18_16mA LVCMOS 1.8 16mA drive, slow slew rate 1.35 1.38 1.42 ns

LVCMOS15_4mA LVCMOS 1.5 4mA drive, slow slew rate 1.57 1.60 1.64 ns

LVCMOS15_8mA LVCMOS 1.5 8mA drive, slow slew rate 0.01 0.01 0.00 ns

LVCMOS12_2mA LVCMOS 1.2 2mA drive, slow slew rate 1.51 1.54 1.58 ns

LVCMOS12_6mA LVCMOS 1.2 6mA drive, slow slew rate -0.02 -0.02 -0.02 ns

PCI33 PCI, VCCIO = 3.0V 0.19 0.21 0.24 ns

1. Timing adders are characterized but not tested on every device.

2. LVCMOS timing measured with the load specified in Switching Test Condition table.

3. All other standards tested according to the appropriate specifications.

4. Not all I/O standards and drive strengths are supported for all banks. See the Architecture section of this data sheet for details.

5. Commercial timing numbers are shown. Industrial numbers are typically slower and can be extracted from the ispLEVER software.

LatticeECP3 Family Timing Adders1, 2, 3, 4, 5 (Continued)

Over Recommended Commercial Operating Conditions

Buffer Type Description -8 -7 -6 Units

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

400 MHz 400 MHz 400 MHz 400 MHz 612 MHz 400 MHz .0 : 3.0v 400 MHz cho : 1.8V 400 MHZ mo : 1.5V 400 MHz ss I. II. cho : aov 400 MHz ssng class I. ll. vCCIO : 2.5V 400 MHz SSTL718 class I. II. cho - .8V 400 MHz LVTTL. vmo : 3.0V 166 MHz LVCMOS. vcmo : 3.0V 166 M LVCMOS. cho 2 2.5V 166 LVCMOS. cho : 1.8V 166 LVCMOS 1.5. cho .5v 166 chmos 1.2. cho .2v 166 PCI. cho 2 3.3V Frequency LVDS. Emulaled. vmo : 2.5V LVDS. cho : 2.5V MLVDS. Emulaled. v00.0 : 2.5V FlSDS. Emulated. vcc.0 : 2.5V BLVDSZS BLVDS. Emulaled. vmo : 2.5V PPLVDS Poml-lo-poinl LVDS LVPECLaa LVPECL. Emulaled. vCCIO Mini-LVDS erll LVDS HSTL18 all supporled classed) HSTLJS class I. II. V HSTL15 all supporled classed HSTLJS class ( ( SSTLBB (all supporled classed ( ( ) ) SSTLJ class SSTLZS all supporled classed) SSTL72 SSTLl 8 all supporled classed) SSTL718 LVTTLBB LV LVCMOSBS (For all dnves) LVCMOSZS (For all dnves) LVCMOST8 (For all drlves) ( ) LVCMOSW 5 For all drlves

3-31

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

LatticeECP3 Maximum I/O Buffer Speed 1, 2, 3, 4, 5, 6

Over Recommended Operating Conditions

Buffer Description Max. Units

Maximum Input Frequency

LVDS 25 LV D S, VCCIO = 2.5V 400 MHz

MLVDS25 MLVDS, Emulated, VCCIO = 2.5V 400 MHz

BLVDS25 BLVDS, Emulated, VCCIO = 2.5V 400 MHz

PPLVDS Point-to-Point LVDS 400 MHz

TRLVDS Transition-Reduced LVDS 612 MHz

Mini LVDS Mini LVDS 400 MHz

LVPECL33 LVPECL, Emulated, VCCIO = 3.0V 400 MHz

HSTL18 (all supported classed) HSTL_18 class I, II, VCCIO = 1.8V 400 MHz

HSTL15 HSTL_15 class I, VCCIO = 1.5V 400 MHz

SSTL33 (all supported classed) SSTL_3 class I, II, VCCIO = 3.0V 400 MHz

SSTL25 (all supported classed) SSTL_2 class I, II, VCCIO = 2.5V 400 MHz

SSTL18 (all supported classed) SSTL_18 class I, II, VCCIO = 1.8V 400 MHz

LVTTL33 LVTTL, VCCIO = 3.0V 166 MHz

LVCM OS33 LVC MOS, VCCIO = 3.0V 166 MHz

LVCM OS25 LVC MOS, VCCIO = 2.5V 166 MHz

LVCM OS18 LVC MOS, VCCIO = 1.8V 166 MHz

LVCMOS15 LVCMOS 1.5, VCCIO = 1.5V 166 MHz

LVCMOS12 LVCMOS 1.2, VCCIO = 1.2V 166 MHz

PCI33 PCI, VCCIO = 3.3V 66 MHz

Maximum Output Frequency

LVDS25E LVDS, Emulated, VCCIO = 2.5V 300 MHz

LVDS 25 LV D S, VCCIO = 2.5V 612 MHz

MLVDS25 MLVDS, Emulated, VCCIO = 2.5V 300 MHz

RSDS25 RSDS, Emulated, VCCIO = 2.5V 612 MHz

BLVDS25 BLVDS, Emulated, VCCIO = 2.5V 300 MHz

PPLVDS Point-to-point LVDS 612 MHz

LVPECL33 LVPECL, Emulated, VCCIO = 3.0V 612 MHz

Mini-LVDS Mini LVDS 612 MHz

HSTL18 (all supported classed) HSTL_18 class I, II, VCCIO = 1.8V 200 MHz

HSTL15 (all supported classed) HSTL_15 class I, VCCIO = 1.5V 200 MHz

SSTL33 (all supported classed) SSTL_3 class I, II, VCCIO = 3.0V 233 MHz

SSTL25 (all supported classed) SSTL_2 class I, II, VCCIO = 2.5V 233 MHz

SSTL18 (all supported classed) SSTL_18 class I, II, VCCIO = 1.8V 266 MHz

LVTTL33 LVTTL, VCCIO = 3.0V 166 MHz

LVCMOS33 (For all drives) LVCMOS, 3.3V 166 MHz

LVCMOS25 (For all drives) LVCMOS, 2.5V 166 MHz

LVCMOS18 (For all drives) LVCMOS, 1.8V 166 MHz

LVCMOS15 (For all drives) LVCMOS, 1.5V 166 MHz

LVCMOS12 (For all drives except 2mA) LVCMOS, VCCIO = 1.2V 166 MHz

LVCMOS12 (2mA drive) LVCMOS, VCCIO = 1.2V 100 MHz

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

66 MHZ m a! «ms document

3-32

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

PCI33 PCI, VCCIO = 3.3V 66 MHz

1. These maximum speeds are characterized but not tested on every device.

2. Maximum I/O speed for differential output standards emulated with resistors depends on the layout.

3. LVCMOS timing is measured with the load specified in the Switching Test Conditions table of this document.

4. All speeds are measured at fast slew.

5. Actual system operation may vary depending on user logic implementation.

6. Maximum data rate equals 2 times the clock rate when utilizing DDR.

LatticeECP3 Maximum I/O Buffer Speed (Continued)1, 2, 3, 4, 5, 6

Over Recommended Operating Conditions

Buffer Description Max. Units

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

2 — 500 MHZ 2 — 420 MHZ dock 4 — 500 MHz Clock 4 — 420 MHZ 0.03125 — 250 MHZ 0.667 — 166 MHZ 500 — 1000 MHZ Edge clock 2 — 500 MHz Primary clock 2 — 420 MHz 65 130 260 p5 Edge dock 45 50 55 % s 250 MHz Pvimary clock 45 50 55 % cm > 250MHz Pvimary clock so 50 7o -5 0 +5 gh or 1.8 — ck penod jmer km 2 420MHz 420MHz >10UT 2100MH2 'om < 100mhz="" inpul="" dock="" 1o="" outpu:="" clock="" skew="" n="" n/m="" :="" integev="" lock="" 1ime="" 210="" 25="" mhz="" 25="" to="" 500="" mhz="" lock="" reset="" io="" pll="" un‘ock="" 1ime="" to="" ensure="" la51="" reset="" input="" clock="" high="" 1ime="" 90%="" 1o="" 90%="" ‘lo="" input="" clock="" low="" time="" 10%="" to="" 10%="" ‘1f‘j1t="" inpul="" clock="" penod="" jillev="" ‘rst="" resel="" signa‘="" pu‘se="" widln="" mgh.="" resetmv="" resetk="" resel="" swgna‘="" pu‘se="" wwdlh="" hxgh,="" cntrst="" f"="" .="" jmer="" samp‘e="" 15="" men="" over10‘000="" samples="" 01="" me="" 2.="" output="" dock="" \s="" vahd="" anev="" «lock="" for="" pll="" reset="" and="" penod="" ﬁner="" and="" cyclerloecyme="" jiner="" number="" 1am="" commons,="" please="" contact="" me="" 1aclory1="">

3-33

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

sysCLOCK PLL Timing

Over Recommended Operating Conditions

Parameter Descriptions Conditions Clock Min. Typ. Max. Units

fIN Input clock frequency (CLKI,

CLKFB) Edge clock 2 — 500 MHz

Primary clock 2 — 420 MHz

fOUT Output clock frequency (CLKOP,

CLKOS) Edge clock 4 — 500 MHz

Primary clock 4 — 420 MHz

fOUT1 K-Divider output frequency CLKOK 0.03125 — 250 MHz

fOUT2 K2-Divider output frequency CLKOK2 0.667 — 166 MHz

fVCO PLL VCO frequency 500 — 1000 MHz

fPFD3Phase detector input frequency Edge clock 2 — 500 MHz

Primary clock 2 — 420 MHz

AC Characteristics

tPA Programmable delay unit 65 130 260 ps

tDT Output clock duty cycle

(CLKOS, at 50% setting)

Edge clock 45 50 55 %

fOUT 250 MHz Primary clock 45 50 55 %

fOUT > 250MHz Primary clock 30 50 70 %

tCPA Coarse phase shift error

(CLKOS, at all settings) -5 0 +5 % of

period

tOPW

Output clock pulse width high or

low

(CLKOS)

1.8 — — ns

tOPJIT1Output clock period jitter

fOUT  420MHz — — 200 p-p

420MHz > fOUT  100MHz — — 250 p-p

fOUT < 100MHz — — 0.025 UIPP

tSK Input clock to output clock skew

when N/M = integer ——500p-p

tLOCK2Lock time 2 to 25 MHz — — 200 us

25 to 500 MHz — — 50 us

tUNLOCK Reset to PLL unlock time to

ensure fast reset — — 50 ns

tHI Input clock high time 90% to 90% 0.5 — — ns

tLO Input clock low time 10% to 10% 0.5 — — ns

tIPJIT Input clock period jitter — — 400 p-p

tRST

Reset signal pulse width high,

RESETM,

RESETK

10 — — ns

Reset signal pulse width high,

CNTRST

500 —— ns

1. Jitter sample is taken over 10,000 samples of the primary PLL output with clean reference clock with no additional I/O toggling.

2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment.

3. Period jitter and cycle-to-cycle jitter numbers are guaranteed for fPFD > 4MHz. For fPFD < 4MHz, the jitter numbers may not be met in cer-

tain conditions. Please contact the factory for fPFD < 4MHz.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

3 — 500 MHZ 133 — 500 MHZ 133 — 500 MHZ 33.3 — 500 MHZ — 200 ps p-p 40 60 ”/0 y Clock 30 7O ”/0 Primary Clock < 250mhz="" 45="" 55="" %="" primary="" clock="" 2="" 250mhz="" 30="" 70="" %="" edge="" clock="" 45="" 55="" %="" levels,="" arbitrary="" primary="" clock="">< 250mhz="" 40="" 60="" %="" ircuit="" .="" 0="" mode)="" with="" dll="" primary="" clock="" 2="" 250mhz="" 30="" 70="" edge="" clock="" 45="" 55="" etween="" two="" outputs="" _="" _="" 100="" at="" device="" pads="" between="" _="" _="" ock="" and="" leedback="" clocks="" +="" nimum="" pulse="" width="" high="" (at="" 80%="" 550="" _="" clock="" minimum="" pulse="" width="" low="" (at="" 20%="" 550="" put="" clock="" period="" jitter="" lock="" lime="" digital="" reset="" minimum="" pulse="" width="" (at="" 80%="" level)="" delay="" step="" size="" max.="" delay="" setting="" for="" single="" delay="" block="" ge‘="" (64="" laps)="" range="" max.="" delay="" setting="" for="" lour="" chained="" delay="" blocks="" 1.="" clkop="" runs="" at="" the="" same="" frequency="" as="" the="" mpm="" clock.="" 2.="" clkos="" minimum="" lrequency="" is="" abtamed="" wmn="" dee="" by="" 4.="" a.="" thls="" is="" intended="" to="" be="" a="" “pathwatcnmg”="" deslgn="" guideline="" and="" is="" not="" a="">

3-34

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

DLL Timing

Over Recommended Operating Conditions

Parameter Description Condition Min. Typ. Max. Units

fREF Input reference clock frequency (on-chip or 

off-chip) 133 — 500 MHz

fFB Feedback clock frequency (on-chip or off-chip) 133 — 500 MHz

fCLKOP1 Output clock frequency, CLKOP 133 — 500 MHz

fCLKOS2 Output clock frequency, CLKOS 33.3 — 500 MHz

tPJIT Output clock period jitter (clean input) — 200 ps p-p

tDUTY

Output clock duty cycle (at 50% levels, 50% duty

cycle input clock, 50% duty cycle circuit turned

off, time reference delay mode)

Edge Clock 40 60 %

Primary Clock 30 70 %

tDUTYTRD

Output clock duty cycle (at 50% levels, arbitrary

duty cycle input clock, 50% duty cycle circuit

enabled, time reference delay mode)

Primary Clock < 250MHz 45 55 %

Primary Clock 250MHz 30 70 %

Edge Clock 45 55 %

tDUTYCIR

Output clock duty cycle (at 50% levels, arbitrary

duty cycle input clock, 50% duty cycle circuit

enabled, clock injection removal mode) with DLL

cascading

Primary Clock < 250MHz 40 60 %

Primary Clock  250MHz 30 70 %

Edge Clock 45 55 %

tSKEW3 Output clock to clock skew between two outputs

with the same phase setting ——100ps

tPHASE Phase error measured at device pads between

off-chip reference clock and feedback clocks — — +/-400 ps

tPWH Input clock minimum pulse width high (at 80%

level) 550 — — ps

tPWL Input clock minimum pulse width low (at 20%

level) 550 — — ps

tINSTB Input clock period jitter — — 500 p-p

tLOCK DLL lock time 8 — 8200 cycles

tRSWD Digital reset minimum pulse width (at 80% level) 3 — — ns

tDEL Delay step size 27 45 70 ps

tRANGE1 Max. delay setting for single delay block 

(64 taps) 1.9 3.1 4.4 ns

tRANGE4 Max. delay setting for four chained delay blocks 7.6 12.4 17.6 ns

1. CLKOP runs at the same frequency as the input clock.

2. CLKOS minimum frequency is obtained with divide by 4.

3. This is intended to be a “path-matching” design guideline and is not a measurable specification.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

1440 1730 mv, p-p 1350 1620 mv, p-p 1000 1260 1510 mv, p-p 840 1130 1420 mv, p-p 730 1040 1300 mv, p-p 690 920 1150 mv, p-p Gbps 650 870 1090 mV, p-p 125 Gbps 585 780 975 mV, p-p lo 3 125 Gbps 480 640 800 mV, p-p _ Vccoa Vccoa Vccoa V -0 75 -0.60 -0.45 — 145 185 265 p5 — 145 185 265 p5 5/HiZ Ohms _ 40% 53/75/ +20% 1 Z 99) — 10 w1|hm a _ _ _ 200 block (inva-quad) skew belween SERDES ocks (Nev-quad) n 50 ohm Impedance. LamceECPS SERDES/PCS Usage Guide lor amual binary semngs and me mmrmax range. ween an SERDES channe1s on the device and requlres me use of a low skew 1n annel Output Jitter Description Frequency Tyn. Delerminisﬁc 3.125 Gbps — — Random 3.125 Gbps — — Total 3.125 Gbps — Determinisﬁc 2.5Gbps — Random 2 5Gbp5 — ToIal 2.5Gbp5 — Determinisﬁc 1.25 Gbps — Random 1 25 Gbps — ToIal 1.25 Gbps — Determinisﬁc 622 Mbps Random 622 Mbps Tolal 622 Mbps Determinisﬁc 250 Mbps Random 250 Mb

3-35

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

SERDES High-Speed Data Transmitter1

Table 3-6. Serial Output Timing and Levels

Table 3-7. Channel Output Jitter

Symbol Description Frequency Min. Typ. Max. Units

VTX-DIFF-P-P-1.44 Differential swing (1.44V setting)1, 2 0.25 to 3.125 Gbps 1150 1440 1730 mV, p-p

VTX-DIFF-P-P-1.35 Differential swing (1.35V setting)1, 2 0.25 to 3.125 Gbps 1080 1350 1620 mV, p-p

VTX-DIFF-P-P-1.26 Differential swing (1.26V setting)1, 2 0.25 to 3.125 Gbps 1000 1260 1510 mV, p-p

VTX-DIFF-P-P-1.13 Differential swing (1.13V setting)1, 2 0.25 to 3.125 Gbps 840 1130 1420 mV, p-p

VTX-DIFF-P-P-1.04 Differential swing (1.04V setting)1, 2 0.25 to 3.125 Gbps 780 1040 1300 mV, p-p

VTX-DIFF-P-P-0.92 Differential swing (0.92V setting)1, 2 0.25 to 3.125 Gbps 690 920 1150 mV, p-p

VTX-DIFF-P-P-0.87 Differential swing (0.87V setting)1, 2 0.25 to 3.125 Gbps 650 870 1090 mV, p-p

VTX-DIFF-P-P-0.78 Differential swing (0.78V setting)1, 2 0.25 to 3.125 Gbps 585 780 975 mV, p-p

VTX-DIFF-P-P-0.64 Differential swing (0.64V setting)1, 2 0.25 to 3.125 Gbps 480 640 800 mV, p-p

VOCM Output common mode voltage — VCCOB

-0.75

VCCOB

-0.60

VCCOB

-0.45 V

TTX-R Rise time (20% to 80%) — 145 185 265 ps

TTX-F Fall time (80% to 20%) — 145 185 265 ps

ZTX-OI-SE Output Impedance 50/75/HiZ Ohms 

(single ended) —-20%

50/75/

Hi Z +20% Ohms

RLTX-RL Return loss (with package) — 10 dB

TTX-INTRASKEW Lane-to-lane TX skew within a 

SERDES quad block (intra-quad) — — — 200 ps

TTX-INTERSKEW3Lane-to-lane skew between SERDES

quad blocks (inter-quad) — — — 1UI +200 ps

1. All measurements are with 50 ohm impedance.

2. See TN1176, LatticeECP3 SERDES/PCS Usage Guide for actual binary settings and the min-max range.

3. Inter-quad skew is between all SERDES channels on the device and requires the use of a low skew internal reference clock.

Description Frequency Min. Typ. Max. Units

Deterministic 3.125 Gbps — — 0.17 UI, p-p

Random 3.125 Gbps — — 0.25 UI, p-p

Total 3.125 Gbps — — 0.35 UI, p-p

Deterministic 2.5Gbps — — 0.17 UI, p-p

Random 2.5Gbps — — 0.20 UI, p-p

Total 2.5Gbps — — 0.35 UI, p-p

Deterministic 1.25 Gbps — — 0.10 UI, p-p

Random 1.25 Gbps — — 0.22 UI, p-p

Total 1.25 Gbps — — 0.24 UI, p-p

Deterministic 622 Mbps — — 0.10 UI, p-p

Random 622 Mbps — — 0.20 UI, p-p

Total 622 Mbps — — 0.24 UI, p-p

Deterministic 250 Mbps — — 0.10 UI, p-p

Random 250 Mbps — — 0.18 UI, p-p

Total 250 Mbps — — 0.24 UI, p-p

Note: Values are measured with PRBS 27-1, all channels operating, FPGA logic active, I/Os around SERDES pins quiet,

reference clock @ 10X mode.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

‘ Fixed ‘Bypass‘ Units HD‘NM of \ H mm n—o mm “mm mm. :17 5.1..“ ‘ 1 1 ‘7 ‘1 l 5 — 1 word clk — — 3 1 word clk 3 5 — — word clk — — 2 1 word c1k — — — 2 1 word dk — — — 15 + A1 — Ul + ps — — — 18 + A1 — Ul + p5 — — — 1 + A2 — Ul + p5 — — — 0 + A3 — Ul + p5 — — — A1 — U — — — A2 — U — — — 10 + A3 — — — — 12 + A3 idge recewe — — — 2 3.1 — 4 — Tolerance Compensaixon 7 15 23 Bridge - Gearing disab‘ed with differeni clocks 1 3 5 FPGA Bridge - Gearing disab‘ed wxih same clocks — — FPGA Bridge - Gearing enab‘ed 1 3 : rzasps, A2 : +aaps, A3 : +112ps. : +11aps. A2 : +132ps‘ A3 : Hoops, ure 3- 12. Transmitter and Receiver Laiency Block Diagra ' H'H'Hsinﬁés'"""V'Vlﬁs'énb'zéiﬁégéﬁl VVVVVVVVVVVVVVVVVVVVVV 1 VVVVVVVVVVVV 1 1 mm em 1 ‘g ‘ \ r’\ r’\ 1 , 1 in 62“ J u x I 1 Q ;

3-36

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

SERDES/PCS Block Latency

Table 3-8 describes the latency of each functional block in the transmitter and receiver. Latency is given in parallel

clock cycles. Figure 3-12 shows the location of each block.

Table 3-8. SERDES/PCS Latency Breakdown

Figure 3-12. Transmitter and Receiver Latency Block Diagram

Item Description Min. Avg. Max. Fixed Bypass Units

Transmit Data Latency1

FPGA Bridge - Gearing disabled with different clocks 1 3 5 — 1 word clk

FPGA Bridge - Gearing disabled with same clocks — — — 3 1 word clk

FPGA Bridge - Gearing enabled 1 3 5 — — word clk

T2 8b10b Encoder — — — 2 1 word clk

T3 SERDES Bridge transmit — — — 2 1 word clk

T4 Serializer: 8-bit mode — — — 15 + 1— UI + ps

Serializer: 10-bit mode — — — 18 + 1— UI + ps

T5 Pre-emphasis ON — — — 1 + 2—UI + ps

Pre-emphasis OFF — — — 0 + 3—UI + ps

Receive Data Latency2

R1 Equalization ON — — — 1—UI + ps

Equalization OFF — — — 2—UI + ps

R2 Deserializer: 8-bit mode — — — 10 + 3— UI + ps

Deserializer: 10-bit mode — — — 12 + 3— UI + ps

R3 SERDES Bridge receive — — — 2 — word clk

R4 Word alignment 3.1 — 4 — — word clk

R5 8b10b decoder — — — 1 — word clk

R6 Clock Tolerance Compensation 7 15 23 1 1 word clk

FPGA Bridge - Gearing disabled with different clocks 1 3 5 — 1 word clk

FPGA Bridge - Gearing disabled with same clocks — — — 3 1 word clk

FPGA Bridge - Gearing enabled 1 3 5 — — word clk

1. 1 = -245ps, 2 = +88ps, 3 = +112ps.

2. 1 = +118ps, 2 = +132ps, 3 = +700ps.

HDOUTPi

HDOUTNi

Deserializer

1:8/1:10

Polarity

Adjust

Elastic

Buffer

FIFO

Encoder

SERDES PCS

BYPASS

Transmitter

Receiver

Recovered Clock

FPGA

Receive Clock

FPGA

Receive Data

Transmit Data

CDR

REFCLK

HDINPi

HDINNi

Polarity

Adjust

Sample

FIFO

SERDES Bridge FPGA Bridge

Serializer

8:1/10:1

WA DEC

FPGA

EBRD Clock

Transmit Clock

TX PLL

REFCLK

FPGA Core

Down

Sample

FIFO

BYPASS

R1 R2 R3 R4 R5 R6

Transmit Clock

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

was 144 160 204 228 296 1760 o vCCA +0.5‘ 0.6 — VCCA 0.1 — VCCA +0.2 — 1ooo — 40% 50/75/HiZ +20% 10 — — on on tne incomlng dala stream when usmg DC coupiing. ck to a new phase or trequency wilhln +/7 300 ppm. assummg amen encoded data. no LVDS. LVDS intertaces are lound m iaserdnvers and Fible Cnannei equlpme DES devices. Tolerance ierate incoming Signal jitter is very dependent on jittertype. Hign sp d the dependency on jitter type and have specifications to indicate t ney reiate to speciﬁc protocols. Sinusoidal jitter is considered to be eceiver Tolal Jilter Tolerance Specification va p-p V V V Bits Ohms dB lion Frequency Condition Min. minislic 600 mV dilierenlial eye — om 3.125 Gbps 600 mV dillerenlial eye — Total 600 mV differential eye Delevminislic 600 mV diﬂerential eye Random 2.5 Gbps 600 mV dillerenlial eye Total 600 mV differenlial eye Delevminislic 600 mV dillerenlial eye Random 1.25 Gbps 600 mV dillerenl Total 600 mV differenl Delevminislic 600 mV di Random 622 Mbps 600 mV di Total 600 Note Vaiues are measured with CJPA'E an en room temperature.

3-37

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

SERDES High Speed Data Receiver

Table 3-9. Serial Input Data Specifications

Input Data Jitter Tolerance

A receiver’s ability to tolerate incoming signal jitter is very dependent on jitter type. High speed serial interface stan-

dards have recognized the dependency on jitter type and have specifications to indicate tolerance levels for differ-

ent jitter types as they relate to specific protocols. Sinusoidal jitter is considered to be a worst case jitter type.

Table 3-10. Receiver Total Jitter Tolerance Specification

Symbol Description Min. Typ. Max. Units

RX-CIDSStream of nontransitions1 

(CID = Consecutive Identical Digits) @ 10-12 BER

3.125G — — 136

Bits

2.5G — — 144

1.485G — — 160

622M — — 204

270M — — 228

155M — — 296

VRX-DIFF-S Differential input sensitivity 150 — 1760 mV, p-p

VRX-IN Input levels 0 — VCCA +0.54V

VRX-CM-DC Input common mode range (DC coupled) 0.6 — VCCA V

VRX-CM-AC Input common mode range (AC coupled)30.1 — VCCA +0.2 V

TRX-RELOCK SCDR re-lock time2—1000—Bits

ZRX-TERM Input termination 50/75 Ohm/High Z -20% 50/75/HiZ +20% Ohms

RLRX-RL Return loss (without package) 10 — — dB

1. This is the number of bits allowed without a transition on the incoming data stream when using DC coupling.

2. This is the typical number of bit times to re-lock to a new phase or frequency within +/- 300 ppm, assuming 8b10b encoded data.

3. AC coupling is used to interface to LVPECL and LVDS. LVDS interfaces are found in laser drivers and Fibre Channel equipment. LVDS int e r -

faces are generally found in 622 Mbps SERDES devices.

4. Up to 1.76V.

Description Frequency Condition Min. Typ. Max. Units

Deterministic

3.125 Gbps

600 mV differential eye — — 0.47 UI, p-p

Random 600 mV differential eye — — 0.18 UI, p-p

Total 600 mV differential eye — — 0.65 UI, p-p

Deterministic

2.5 Gbps

600 mV differential eye — — 0.47 UI, p-p

Random 600 mV differential eye — — 0.18 UI, p-p

Total 600 mV differential eye — — 0.65 UI, p-p

Deterministic

1.25 Gbps

600 mV differential eye — — 0.47 UI, p-p

Random 600 mV differential eye — — 0.18 UI, p-p

Total 600 mV differential eye — — 0.65 UI, p-p

Deterministic

622 Mbps

600 mV differential eye — — 0.47 UI, p-p

Random 600 mV differential eye — — 0.18 UI, p-p

Total 600 mV differential eye — — 0.65 UI, p-p

Note: Values are measured with CJPAT, all channels operating, FPGA Logic active, I/Os around SERDES pins quiet, voltages are nominal,

room temperature.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

0.22 Ul‘ p-p 0.24 Ul, p-p — 0.15 Ul, p-p — 0.5 Ul‘ p-p acuve, U05 around SEHDES pms

3-38

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

Table 3-11. Periodic Receiver Jitter Tolerance Specification

Description Frequency Condition Min. Typ. Max. Units

Periodic 2.97 Gbps 600 mV differential eye — — 0.24 UI, p-p

Periodic 2.5 Gbps 600 mV differential eye — — 0.22 UI, p-p

Periodic 1.485 Gbps 600 mV differential eye — — 0.24 UI, p-p

Periodic 622 Mbps 600 mV differential eye — — 0.15 UI, p-p

Periodic 155 Mbps 600 mV differential eye — — 0.5 UI, p-p

Note: Values are measured with PRBS 27-1, all channels operating, FPGA Logic active, I/Os around SERDES pins

quiet, voltages are nominal, room temperature.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

Max. Units 320 MHZ — 1000 ppm — VCCA "N P-P _ 2‘VCC" dmglr‘egn‘igl — vCCA + 0.3 v o 125 — vGOA v 40 — 60 °/a 200 500 1000 p5 200 500 1000 p5 -20°/o 100/2K +20% Ohms — — 7 pF st be as large as me pap dlﬂerenllal swmg a! a dmerenhal mpm clock to ge: the s ck may be possuble. but w‘m :end to morease mar range Is determined by: ng)/2 : Unput common mode vanage) : (Max mpul have” , (Peakrmrpeak mpm sw LLiLOLisET and CDFLLOLisET control registers may be adjusted {or Other tol LamceECPa SERDES/PCS Usage Gulde External Reference Clack Wavefnrms r:\ t ‘, \, w.’ ." 7 74 , 77 7 7 ' an I \ \ ‘ n a 77 ‘ v

3-39

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

SERDES External Reference Clock

The external reference clock selection and its interface are a critical part of system applications for this product.

Table 3-12 specifies reference clock requirements, over the full range of operating conditions.

Figure 3-13. SERDES External Reference Clock Waveforms

Table 3-12. External Reference Clock Specification (refclkp/refclkn)

Symbol Description Min. Typ. Max. Units

FREF Frequency range 15 — 320 MHz

FREF-PPM Frequency tolerance4-1000 — 1000 ppm

VREF-IN-SE Input swing, single-ended clock1200 — VCCA mV, p-p

VREF-IN-DIFF Input swing, differential clock 200 — 2*VCCA mV, p-p

differential

VREF-IN Input levels 0 — VCCA + 0.3 V

VREF-CM-AC Input common mode range (AC coupled)20.125 — VCCA V

DREF Duty cycle340 — 60 %

TREF-R Rise time (20% to 80%) 200 500 1000 ps

TREF-F Fall time (80% to 20%) 200 500 1000 ps

ZREF-IN-TERM-DIFF Differential input termination -20% 100/2K +20% Ohms

CREF-IN-CAP Input capacitance — — 7 pF

1. The signal swing for a single-ended input clock must be as large as the p-p differential swing of a differential input clock to get the same gain

at the input receiver. Lower swings for the clock may be possible, but will tend to increase jitter.

2. When AC coupled, the input common mode range is determined by: 

(Min input level) + (Peak-to-peak input swing)/2  (Input common mode voltage)  (Max input level) - (Peak-to-peak input swing)/2

3. Measured at 50% amplitude.

4. Depending on the application, the PLL_LOL_SET and CDR_LOL_SET control registers may be adjusted for other tolerance values as

described in TN1176, LatticeECP3 SERDES/PCS Usage Guide.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

n ‘ Typ ‘ Max Units 399 88 400 40012 ps 0 8 1.0 1 .2 V -3 -3.5 -4 dB — — 20 mV lowed duv- _ _ 600 mV ge 0 — V0003 + 5% V — — 90 mA impedance 80 100 120 Ohms n loss 10 — — mode velum loss 6.0 — — ise lime 20 to 80% 0.125 — — ipui lall lime 20 lo 80% 0.125 — — e-io-lane static oulpui skew fov all _ _ lanes in porI/lmk Transmxller eye widlh 0 75 lWER Maximum llme belween jinev median and maximum deviaiion from median Unit lnierval IFFiP-P Dillerenlial peak»lo-peak inpul voltage DLE-DEr-DlFFj-P ldle deleci ihreshold vollage Receiver common mode voliage lor AC X-CM-ACJ? coupling FlX-DlFF-DC DC diﬂerenlial inpul impedance ZFlX-DC DC inpui impedance ZFlX-HlGH-lMF-DC Powev-down DC input impedance RLFlX-DIFF Dillerenlial Ielum loss RLFlX-CM Common mode velum loss TFlX-lDLE-DEFDlFF-ENTERTlME Maximum llme veqmve recognize and signal a on link 1. Values are measured ai 2.5 Gbps. 2. Measured wllh exlemal ACrcoupllng on me 3.Nol m compliance wllh PCI Express 1.1 slan

3-40

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

PCI Express Electrical and Timing Characteristics

AC and DC Characteristics

Over Recommended Operating Conditions

Symbol Description Test Conditions Min Typ Max Units

Transmit1

UI Unit interval 399.88 400 400.12 ps

VTX-DIFF_P-P Differential peak-to-peak output voltage 0.8 1.0 1.2 V

VTX-DE-RATIO De-emphasis differential output voltage

ratio -3 -3.5 -4 dB

VTX-CM-AC_P RMS AC peak common-mode output

voltage —— 20 mV

VTX-RCV-DETECT Amount of voltage change allowed dur-

ing receiver detection —— 600 mV

VTX-DC-CM Tx DC common mode voltage 0 — VCCOB + 5% V

ITX-SHORT Output short circuit current VTX-D+=0.0V

VTX-D-=0.0V —— 90 mA

ZTX-DIFF-DC Differential output impedance 80 100 120 Ohms

RLTX-DIFF Differential return loss 10 — — dB

RLTX-CM Common mode return loss 6.0 — — dB

TTX-RISE Tx output rise time 20 to 80% 0.125 — — UI

TTX-FALL Tx output fall time 20 to 80% 0.125 — — UI

LTX-SKEW Lane-to-lane static output skew for all

lanes in port/link —— 1.3 ns

TTX-EYE Transmitter eye width 0.75 — — UI

TTX-EYE-MEDIAN-TO-MAX-JITTER Maximum time between jitter median

and maximum deviation from median — — 0.125 UI

Receive1, 2

UI Unit Interval 399.88 400 400.12 ps

VRX-DIFF_P-P Differential peak-to-peak input voltage 0.343—1.2V

VRX-IDLE-DET-DIFF_P-P Idle detect threshold voltage 65 — 3403mV

VRX-CM-AC_P Receiver common mode voltage for AC

coupling —— 150 mV

ZRX-DIFF-DC DC differential input impedance 80 100 120 Ohms

ZRX-DC DC input impedance 40 50 60 Ohms

ZRX-HIGH-IMP-DC Power-down DC input impedance 200K — — Ohms

RLRX-DIFF Differential return loss 10 — — dB

RLRX-CM Common mode return loss 6.0 — — dB

TRX-IDLE-DET-DIFF-ENTERTIME

Maximum time required for receiver to

recognize and signal an unexpected idle

on link

—— — ms

1. Values are measured at 2.5 Gbps.

2. Measured with external AC-coupling on the receiver.

3.Not in compliance with PCI Express 1.1 standard.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

Max. 120 017 035 hm Impedance (tOOVonm aitterenlial Impedance). 50% threshold of the reteience Slgnal mended Operating Conditions Test Conditions Min. Typ. Max. U From 100 MHz 10 _ _ to 3 125 GHZ From 100 MHz ” “’55 to 3.125 GHZ e _ _ ination resistance 80 100 nlstlc jitter tolerance (peak-to-peak) — — om jitter tolerance (peak-to-peak) — — nusoidal jitter tolerance (peak-to-peak) — Total jitter tolerance (peak-to-peak) — Receiver eye opening Includes determinlstlc jlﬂen random jitter and Sinusmdal jitter The sinusmdal jitter to tiles are measured with each highrspeed input AC coupled into a Soronm lmpeda er and skew are speciﬁed between allterential crossings of the 50% threshold ot the r er tolerance parameters are characterized when Full Rx Equalization is enable Values are measured at 2,5 Gbps.

3-41

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

XAUI/Serial Rapid I/O Type 3 Electrical and Timing Characteristics

AC and DC Characteristics

Table 3-13. Transmit

Over Recommended Operating Conditions

Table 3-14. Receive and Jitter Tolerance

Over Recommended Operating Conditions

Symbol Description Test Conditions Min. Typ. Max. Units

TRF Differential rise/fall time 20%-80% — 80 — ps

ZTX_DIFF_DC Differential impedance 80 100 120 Ohms

JTX_DDJ2, 3, 4 Output data deterministic jitter — — 0.17 UI

JTX_TJ1, 2, 3, 4 Total output data jitter — — 0.35 UI

1. Total jitter includes both deterministic jitter and random jitter.

2. Jitter values are measured with each CML output AC coupled into a 50-ohm impedance (100-ohm differential impedance).

3. Jitter and skew are specified between differential crossings of the 50% threshold of the reference signal.

4. Values are measured at 2.5 Gbps.

Symbol Description Test Conditions Min. Typ. Max. Units

RLRX_DIFF Differential return loss From 100 MHz

to 3.125 GHz 10 — — dB

RLRX_CM Common mode return loss From 100 MHz

to 3.125 GHz 6——dB

ZRX_DIFF Differential termination resistance 80 100 120 Ohms

JRX_DJ1, 2, 3 Deterministic jitter tolerance (peak-to-peak) — — 0.37 UI

JRX_RJ1, 2, 3 Random jitter tolerance (peak-to-peak) — — 0.18 UI

JRX_SJ1, 2, 3 Sinusoidal jitter tolerance (peak-to-peak) — — 0.10 UI

JRX_TJ1, 2, 3 Total jitter tolerance (peak-to-peak) — — 0.65 UI

TRX_EYE Receiver eye opening 0.35 — — UI

1. Total jitter includes deterministic jitter, random jitter and sinusoidal jitter. The sinusoidal jitter tolerance mask is shown in Figure 3-14.

2. Jitter values are measured with each high-speed input AC coupled into a 50-ohm impedance.

3. Jitter and skew are specified between differential crossings of the 50% threshold of the reference signal.

4. Jitter tolerance parameters are characterized when Full Rx Equalization is enabled.

5. Values are measured at 2.5 Gbps.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

‘mUI —A—A_. 9/ 20M HZ 1667 uency ed mm a| \east 0 37U|pp of Determmlstlc dam men \s m \eas\ o 55U‘pp Thevelme. (he s m least a 65Ulpp (D1 = o 37 R] = o 18, 5] =01)

3-42

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

Figure 3-14. XAUI Sinusoidal Jitter Tolerance Mask

Note: The sinusoidal jitter tolerance is measured with at least 0.37UIpp of Deterministic

jitter (Dj) and the sum of Dj and Rj (random jitter) is at least 0.55UIpp. Therefore, the

sum of Dj, Rj and Sj (sinusoidal jitter) is at least 0.65UIpp (Dj = 0.37, Rj = 0.18, Sj = 0.1).

Data_rate/

1667

20MHz

20dB/dec

8.5UI

SJ Amplitude

SJ Frequency

0.1UI

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

Max. 120 0.17 0.35 cad, me Iota‘ Inter mlnus the actual determumshc ﬁner. Impedance (100mm dmerenhal Impedance). resnom or me recerence swgna‘ Test Conditions Min. Typ. Max. Unils From 100 MHZ to 2.5 GHZ 1O — — dB From 100 MHzto 2 5 GHz 6 — — resistance 80 100 120 \evance (peak-m-peak) — — 0. lerance (peak-to-peak) — — 0. rance (peak-lo-peak) — — lerance (peak-lo-peak) — — r eye opening 0.35 rmmsnc jlﬂef. random mer and sinusoxda‘ jlﬂef The smusoudal mermxemnoe sured wmn each mghrspeed mpm AC coupled mo a 50mm impedance, are specmed belween differenna‘ crossmgs a! me 50% mresnola ofthe recerence sxgn e. Dmererma‘ Input Sensiuwy and Hecewer Eye Opemng pavameters are charact e measured at 2.5 Gbps

3-43

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

Serial Rapid I/O Type 2 Electrical and Timing Characteristics

AC and DC Characteristics

Table 3-15. Transmit

Table 3-16. Receive and Jitter Tolerance

Symbol Description Test Conditions Min. Typ. Max. Units

TRF1Differential rise/fall time 20%-80% — 80 — ps

ZTX_DIFF_DC Differential impedance 80 100 120 Ohms

JTX_DDJ3, 4, 5 Output data deterministic jitter — — 0.17 UI

JTX_TJ2, 3, 4, 5 Total output data jitter — — 0.35 UI

1. Rise and Fall times measured with board trace, connector and approximately 2.5pf load.

2. Total jitter includes both deterministic jitter and random jitter. The random jitter is the total jitter minus the actual deterministic jitter.

3. Jitter values are measured with each CML output AC coupled into a 50-ohm impedance (100-ohm differential impedance).

4. Jitter and skew are specified between differential crossings of the 50% threshold of the reference signal.

5. Values are measured at 2.5 Gbps.

Symbol Description Test Conditions Min. Typ. Max. Units

RLRX_DIFF Differential return loss From 100 MHz to 2.5 GHz 10 — — dB

RLRX_CM Common mode return loss From 100 MHz to 2.5 GHz 6 — — dB

ZRX_DIFF Differential termination resistance 80 100 120 Ohms

JRX_DJ2, 3, 4, 5 Deterministic jitter tolerance (peak-to-peak) — — 0.37 UI

JRX_RJ2, 3, 4, 5 Random jitter tolerance (peak-to-peak) — — 0.18 UI

JRX_SJ2, 3, 4, 5 Sinusoidal jitter tolerance (peak-to-peak) — — 0.10 UI

JRX_TJ1, 2, 3, 4, 5 Total jitter tolerance (peak-to-peak) — — 0.65 UI

TRX_EYE Receiver eye opening 0.35 — — UI

1. Total jitter includes deterministic jitter, random jitter and sinusoidal jitter. The sinusoidal jitter tolerance mask is shown in Figure 3-14.

2. Jitter values are measured with each high-speed input AC coupled into a 50-ohm impedance.

3. Jitter and skew are specified between differential crossings of the 50% threshold of the reference signal.

4. Jitter tolerance, Differential Input Sensitivity and Receiver Eye Opening parameters are characterized when Full Rx Equalization is enabled.

5. Values are measured at 2.5 Gbps.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

Typ. Max. 80 — 120 0.10 0.24 2.5m load er Is me Iota‘ mter mmus me actual determumshmmen Orohm Impedance (1007mm unnerenual Impedance). 50% mresnom or me recerence swgna‘. Test Conditions Min. Typ. Max. Unils From 100 MHZ to 1.25 GHZ 1O — — From 100 MHz to 1 25 GHz 6 — — vesxstance 80 100 1 erance (peak-to-peak) — — O rance (peak-Io-peak) _ _ jxuev Io‘evance (peakm-peak) _ _ Io‘evance (peak-ko-peak) — ver eye opemng es delermxmsﬂc jlﬂef. randam mer and sinusoida‘ mer The sinusouda‘ ﬁner to‘erance measured wmn each mghspeeu mpm AC caup‘ed mo a 50mm Impedance, skew are specmed between dMeremial crossmgs at me 50% mreshom of me receren rance. Dmerenhal \npm Sensmvny and Reeewer Eye Opemng parameners are charac are measured at 125 Gbps.

3-44

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

Gigabit Ethernet/Serial Rapid I/O Type 1/SGMII Electrical and Timing 

Characteristics

AC and DC Characteristics

Table 3-17. Transmit

Table 3-18. Receive and Jitter Tolerance

Symbol Description Test Conditions Min. Typ. Max. Units

TRF Differential rise/fall time 20%-80% — 80 — ps

ZTX_DIFF_DC Differential impedance 80 100 120 Ohms

JTX_DDJ3, 4, 5 Output data deterministic jitter — — 0.10 UI

JTX_TJ2, 3, 4, 5 Total output data jitter — — 0.24 UI

1. Rise and fall times measured with board trace, connector and approximately 2.5pf load.

2. Total jitter includes both deterministic jitter and random jitter. The random jitter is the total jitter minus the actual deterministic jitter.

3. Jitter values are measured with each CML output AC coupled into a 50-ohm impedance (100-ohm differential impedance).

4. Jitter and skew are specified between differential crossings of the 50% threshold of the reference signal.

5. Values are measured at 1.25 Gbps.

Symbol Description Test Conditions Min. Typ. Max. Units

RLRX_DIFF Differential return loss From 100 MHz to 1.25 GHz 10 — — dB

RLRX_CM Common mode return loss From 100 MHz to 1.25 GHz 6 — — dB

ZRX_DIFF Differential termination resistance 80 100 120 Ohms

JRX_DJ1, 2, 3, 4, 5 Deterministic jitter tolerance (peak-to-peak) — — 0.34 UI

JRX_RJ1, 2, 3, 4, 5 Random jitter tolerance (peak-to-peak) — — 0.26 UI

JRX_SJ1, 2, 3, 4, 5 Sinusoidal jitter tolerance (peak-to-peak) — — 0.11 UI

JRX_TJ1, 2, 3, 4, 5 Total jitter tolerance (peak-to-peak) — — 0.71 UI

TRX_EYE Receiver eye opening 0.29 — — UI

1. Total jitter includes deterministic jitter, random jitter and sinusoidal jitter. The sinusoidal jitter tolerance mask is shown in Figure 3-14.

2. Jitter values are measured with each high-speed input AC coupled into a 50-ohm impedance.

3. Jitter and skew are specified between differential crossings of the 50% threshold of the reference signal.

4. Jitter tolerance, Differential Input Sensitivity and Receiver Eye Opening parameters are characterized when Full Rx Equalization is enabled.

5. Values are measured at 1.25 Gbps.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

Max. Units 2975 Mbps 0.20 Ui 0.20 Ui 0.30 Ui 0.20 Ui 1.0 Ui 2.0 Ul 996, SMPTE RP19271996 and me applicabie senai uaia lransmissmn sianr bar test paiiem is used The value oi iSCLK Is 270 MHz or 360 MHz ior for SMPTE 292M senai daia rates. See the Timing .Jmer Bandpass secnon 96 as liner ai an equipmem auipui m lhe absence oi Inpui mien sianuara cable drlver; connection in me came driver Is via a 50 ohm Impedance :1 led 31270.1485mr2970 Mbps. RREFLVL:RREFPRE:4 75kohm1%. riplion Min. Typ. raie 270 — 7(SG)/26(SMPTE non-iransitions . ecuiive Identical Digiis) @‘i’ri1pge1rzalaegn . Reference Clack mbol Description Test Conditions VCLK Video ouipui ciock frequency DCV Duly cycie, video clock

3-45

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

SMPTE SD/HD-SDI/3G-SDI (Serial Digital Interface) Electrical and Timing

Characteristics

AC and DC Characteristics

Table 3-19. Transmit

Table 3-20. Receive

Table 3-21. Reference Clock

Symbol Description Test Conditions Min. Typ. Max. Units

BRSDO Serial data rate 270 — 2975 Mbps

TJALIGNMENT 2 Serial output jitter, alignment 270 Mbps — — 0.20 UI

TJALIGNMENT 2 Serial output jitter, alignment 1485 Mbps — — 0.20 UI

TJALIGNMENT1, 2 Serial output jitter, alignment 2970Mbps — — 0.30 UI

TJTIMING Serial output jitter, timing 270 Mbps — — 0.20 UI

TJTIMING Serial output jitter, timing 1485 Mbps — — 1.0 UI

TJTIMING Serial output jitter, timing 2970 Mbps — — 2.0 UI

Notes:

1. Timing jitter is measured in accordance with SMPTE RP 184-1996, SMPTE RP 192-1996 and the applicable serial data transmission stan-

dard, SMPTE 259M-1997 or SMPTE 292M (proposed). A color bar test pattern is used.The value of fSCLK is 270 MHz or 360 MHz for

SMPTE 259M, 540 MHz for SMPTE 344M or 1485 MHz for SMPTE 292M serial data rates. See the Timing Jitter Bandpass section.

2. Jitter is defined in accordance with SMPTE RP1 184-1996 as: jitter at an equipment output in the absence of input jitter.

3. All Tx jitter is measured at the output of an industry standard cable driver; connection to the cable driver is via a 50 ohm impedance differen-

tial signal from the Lattice SERDES device.

4. The cable driver drives: RL=75 ohm, AC-coupled at 270, 1485, or 2970 Mbps, RREFLVL=RREFPRE=4.75kohm 1%.

Symbol Description Test Conditions Min. Typ. Max. Units

BRSDI Serial input data rate 270 — 2970 Mbps

CID Stream of non-transitions

(=Consecutive Identical Digits)

7(3G)/26(SMPTE

Triple rates)

@ 10-12 BER

——Bits

Symbol Description Test Conditions Min. Typ. Max. Units

FVCLK Video output clock frequency 27 — 74.25 MHz

DCVDuty cycle, video clock 45 50 55 %

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

Spec. Compliance Min. Spec. Max. Spec. Units — 75 ps — 800 p5 — 0.25 Ul 40 60 Ohms de Voltage (SO-ohm Semng) — 50 mV — 0 25 UI d IS zebps, IHransIauon dewce dues not "10le use/tan hme. me maXImum speed n me 3,3v common made Germany, HDMI Inputs are «erminama ny an externa‘ ceECP3 device

3-46

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

HDMI (High-Definition Multimedia Interface) Electrical and Timing 

Characteristics

AC and DC Characteristics

Table 3-22. Transmit and Receive1, 2

Symbol Description

Spec. Compliance

UnitsMin. Spec. Max. Spec.

Transmit

Intra-pair Skew —75ps

Inter-pair Skew — 800 ps

TMDS Differential Clock Jitter — 0.25 UI

Receive

RTTermination Resistance 40 60 Ohms

VICM Input AC Common Mode Voltage (50-ohm Setting) — 50 mV

TMDS Clock Jitter Clock Jitter Tolerance — 0.25 UI

1. Output buffers must drive a translation device. Max. speed is 2Gbps. If translation device does not modify rise/fall time, the maximum speed

is 1.5Gbps.

2. Input buffers must be AC coupled in order to support the 3.3V common mode. Generally, HDMI inputs are terminated by an external cable

equalizer before data/clock is forwarded to the LatticeECP3 device.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

E} F : 759 5 5-3on- m 50 |est eqm (ausunauan 3.5«45’ 1 OuF ”‘35“ ‘Rvsehme wmvensahan Iller Bandpass oab, , Passband thple < 2165="" jiller="" bandpass="" rejecmn="" jlﬂer="" fre="">

3-47

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

Figure 3-15. Test Loads

Jitter Bandpass

Jitter Frequency

0db

VDDIO

CLIOH

IOL

CMOS

outputs

Test Loads

Timing Jitter Bandpass

Hi-Z test eqpt. ≥ 5Ωk

(atteunation 0dB)

CL including probe and jig capacitance, 3pF max.

S1 - open, S2 - closed for VOH measurement.

S1 - closed, S2 - open for VOL measurement.

10Hz

Passband Ripple

< ±1dB

Stopband

Rejection

<20dB

Slopes:

20dB/Decade

>1/10 fSCLK

VDDSD

SDO

1.0µF

75Ω test eqpt.

(atteunation 0dB)

75Ω

VDDSD

SDO

1.0µF

*Risetime compensation.

24.9Ω

5.5-30pF*

50 test eqpt.

(atteunation 3.5dB)

75Ω

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

— 23 ms ave mode — 6 ms — 5 us 25 — ns — 10 ns — 37 ns — 37 ns — 1 ms DONE Pin is High 100 500 cycles — 300 ns 5 — ns 1 _ owlniougn Mode — 12 lse Pulse uency Withoul encryplion With encryplion rallel own 0] Setup Time to CCLK/MCLK CSNU 0] Hold Time to CCLK/MCLK WRlTEN Setup Time to CCLK/MCLK WRlTEN Hold Time I0 CCLK/MCLK CCLK/MCLK to BUSV Delay Time CCLK to Out foi Flead Dala om) [BSCH CCLK Minimum High Pulse [55m CCLK Minimum Low Pulse tascvc Byte Slave Cycle Time foam CCLK/MCLK Frequency Master and Slave SPI [CFGX lNlTN High to MCLK Low i059. lNlTN High m CSSPIN Low [some MCLK Low lo Oulpul Valid [55pm CSSPlN[O'1] Lowlo Firsl MC iCCLK CCLK Frequency

3-48

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

LatticeECP3 sysCONFIG Port Timing Specifications

Over Recommended Operating Conditions

Parameter Description Min. Max. Units

POR, Configuration Initialization, and Wakeup

tICFG

Time from the Application of VCC, VCCAUX or VCCIO8* (Whichever

is the Last to Cross the POR Trip Point) to the Rising Edge of

INITN

Master mode — 23 ms

Slave mode — 6 ms

tVMC Time from tICFG to the Valid Master MCLK — 5 µs

tPRGM PROGRAMN Low Time to Start Configuration 25 — ns

tPRGMRJ PROGRAMN Pin Pulse Rejection — 10 ns

tDPPINIT Delay Time from PROGRAMN Low to INITN Low — 37 ns

tDPPDONE Delay Time from PROGRAMN Low to DONE Low — 37 ns

tDINIT PROGRAMN High to INITN High Delay — 1 ms

tMWC Additional Wake Master Clock Signals After DONE Pin is High 100 500 cycles

tCZ MCLK From Active To Low To High-Z — 300 ns

All Configuration Modes

tSUCDI Data Setup Time to CCLK/MCLK 5 — ns

tHCDI Data Hold Time to CCLK/MCLK 1 — ns

tCODO CCLK/MCLK to DOUT in Flowthrough Mode — 12 ns

Slave Serial

tSSCH CCLK Minimum High Pulse 5 — ns

tSSCL CCLK Minimum Low Pulse 5 — ns

fCCLK CCLK Frequency Without encryption — 33 MHz

With encryption — 20 MHz

Master and Slave Parallel

tSUCS CSN[1:0] Setup Time to CCLK/MCLK 7 — ns

tHCS CSN[1:0] Hold Time to CCLK/MCLK 1 — ns

tSUWD WRITEN Setup Time to CCLK/MCLK 7 — ns

tHWD WRITEN Hold Time to CCLK/MCLK 1 — ns

tDCB CCLK/MCLK to BUSY Delay Time — 12 ns

tCORD CCLK to Out for Read Data — 12 ns

tBSCH CCLK Minimum High Pulse 6 — ns

tBSCL CCLK Minimum Low Pulse 6 — ns

tBSCYC Byte Slave Cycle Time 30 — ns

fCCLK CCLK/MCLK Frequency Without encryption — 33 MHz

With encryption — 20 MHz

Master and Slave SPI

tCFGX INITN High to MCLK Low — 80 ns

tCSSPI INITN High to CSSPIN Low 0.2 2 µs

tSOCDO MCLK Low to Output Valid — 15 ns

tCSPID CSSPIN[0:1] Low to First MCLK Edge Setup Time 0.3 µs

fCCLK CCLK Frequency Without encryption — 33 MHz

With encryption — 20 MHz

tSSCH CCLK Minimum High Pulse 5 — ns

tSSCL CCLK Minimum Low Pulse 5 — ns

tHLCH HOLDN Low Setup Time (Relative to CCLK) 5 — ns

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

Max. Units Selected value + 15% MHZ 60 % WFUTEN BUSY ma 7] ycle ‘n 7 wasx byte 0' mad cyde

3-49

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

Figure 3-16. sysCONFIG Parallel Port Read Cycle

tCHHH HOLDN Low Hold Time (Relative to CCLK) 5 — ns

Master and Slave SPI (Continued)

tCHHL HOLDN High Hold Time (Relative to CCLK) 5 — ns

tHHCH HOLDN High Setup Time (Relative to CCLK) 5 — ns

tHLQZ HOLDN to Output High-Z — 9 ns

tHHQX HOLDN to Output Low-Z — 9 ns

Parameter Min. Max. Units

Master Clock Frequency Selected value - 15% Selected value + 15% MHz

Duty Cycle 40 60 %

LatticeECP3 sysCONFIG Port Timing Specifications (Continued)

Over Recommended Operating Conditions

Parameter Description Min. Max. Units

CCLK

CS1N

CSN

WRITEN

BUSY

D[0:7]

tSUCS tHCS

tSUWD

tCORD

tDCB

tHWD

tBSCYC

tBSCH

tBSCL

Byte 0 Byte 1 Byte 2 Byte n*

*n = last byte of read cycle.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

H l * 1m l ‘7 >15an -_aa wags CCLK (MCLK) In Slave Parallel Mode the external device pmvldes CCLK. rial Pan Timing c m gum if 1mm DIN X | f ‘copo X i T 9 3-19. sysCONFIG Slave Serial Port Timing [55m 4+7 CCLK lmpul) [mm + Alf DIN I I» | I DOUT

3-50

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

Figure 3-17. sysCONFIG Parallel Port Write Cycle

Figure 3-18. sysCONFIG Master Serial Port Timing

Figure 3-19. sysCONFIG Slave Serial Port Timing

CCLK

CS1N

CSN

WRITEN

BUSY

D[0:7]

tSUCS tHCS

tSUWD

tHCBDI

tDCB

tHWD

tBSCYC

tBSCH

tBSCL

tSUCBDI

Byte 0 Byte 1 Byte 2 Byte n

1. In Master Parallel Mode the FPGA provides CCLK (MCLK). In Slave Parallel Mode the external device provides CCLK.

CCLK (output)

DIN

DOUT

tSUMCDI

tHMCDI

tCODO

CCLK (input)

DIN

DOUT

tSUSCDI

tHSCDI

tCODO

tSSCL tSSCH

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

v er ws me \as| to mass the FOR my palm. (u; Linc . '1 - -| VCC -. b—u—IW. I ccu< (hr-m1="" “\“j="" n="" n:="" (ogramn="" law="" i="" :="" imm="" .="" initn="" '="" :‘flth-j="" (mac="" ))="" '="" done="" 1%="" n="" (m="" u)="" "i="" .="" *="" 1“”me="" di="" i="" dout="" :="" .="" i="" i="" i="" syslo="" '="" .="" lam="" .="" i="" mm="" mm="" rm.="" m="" comm="" mm="" w="" m="">

3-51

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

Figure 3-20. Power-On-Reset (POR) Timing

Figure 3-21. sysCONFIG Port Timing

CCLK 2

DONE

VCC / VCCAUX /

VCCIO81

CFG[2:0] 3

tICFG

Valid

INITN

tVMC

1. Time taken from VCC, VCCAUX or VCCIO8, whichever is the last to cross the POR trip point.

2. Device is in a Master Mode (SPI, SPIm).

3. The CFG pins are normally static (hard wired).

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

H HH‘ Vahd d med) \TN DONE Wake»Up CCLK m1: hams: USER l/O

3-52

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

Figure 3-22. Configuration from PROGRAMN Timing

Figure 3-23. Wake-Up Timing

DONE

CCLK

CFG[2:0]1

USER I/O

INITN

PROGRAMN

tPRGMRJ

tDINIT

tDPPINIT

tDINITD

tIODISS

Valid

1. The CFG pins are normally static (hard wired)

CCLK

DONE

PROGRAMN

USER I/O

INITN

tIOENSS

Wake-Up

tMWC

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

Ea‘q ”233313 ‘7‘25 Addvess \gnore Vahd ansueam

3-53

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

Figure 3-24. Master SPI Configuration Waveforms

Opcode Address

0 1 2 3 … 7 8 9 10 … 31 32 33 34 … 127 128

VCC

PROGRAMN

DONE

INITN

CSSPIN

CCLK

SISPI

SOSPI

Capture CFGx

Capture CR0

Ignore Valid Bitstream

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

TCK TDO Dala m be caplured lmm l/O — 25 MHZ 40 — ns 20 — ns 20 — ns 10 — n5 8 — ns 50 — mV/ns — 10 n5 isable — 10 ns nable — 10 n5 8 — n5 llme 25 — n5 ng edge of clock lo valid output — 25 n5 r. lalling edge of clock to valid disable — 25 n5 lsler. lalling edge of clock lo valid enable — 25 Waveforms ‘ETS +<7 ‘eth="" ‘etcph="" 4",="" 13mm="" 4»="" ‘etcoen="">

3-54

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

JTAG Port Timing Specifications

Over Recommended Operating Conditions

Figure 3-25. JTAG Port Timing Waveforms

Symbol Parameter Min Max Units

fMAX TCK clock frequency — 25 MHz

tBTCP TCK [BSCAN] clock pulse width 40 — ns

tBTCPH TCK [BSCAN] clock pulse width high 20 — ns

tBTCPL TCK [BSCAN] clock pulse width low 20 — ns

tBTS TCK [BSCAN] setup time 10 — ns

tBTH TCK [BSCAN] hold time 8 — ns

tBTRF TCK [BSCAN] rise/fall time 50 — mV/ns

tBTCO TAP controller falling edge of clock to valid output — 10 ns

tBTCODIS TAP controller falling edge of clock to valid disable — 10 ns

tBTCOEN TAP controller falling edge of clock to valid enable — 10 ns

tBTCRS BSCAN test capture register setup time 8 — ns

tBTCRH BSCAN test capture register hold time 25 — ns

tBUTCO BSCAN test update register, falling edge of clock to valid output — 25 ns

tBTUODIS BSCAN test update register, falling edge of clock to valid disable — 25 ns

tBTUPOEN BSCAN test update register, falling edge of clock to valid enable — 25 ns

TMS

TDI

TCK

TDO

Data to be

captured

from I/O

Data to be

driven out

to I/O

ataD dilaVataD dilaV

Data Captured

BTCPH

BTCPL

BTCOEN

BTCRS

BTUPOEN

BUTCO

BTUODIS

BTCRH

BTCO

BTCODIS

BTS

BTH

BTCP

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

ﬁxture and Probe Capacnance 0 Test Poi nt % 4% if nenls, Non-Terminated lmerfaces R1 R2 CL Timing Rel. LVCMOS 3.3 : 1.5V LVCMOS 2.5 : vCCIO mngs (L -> H, H -> L) w 00 OpF LVCMOS 1.8 : vCCIO LVCMOS 1.5 : LVCMOS 1.2 : (z -> H) so 1M9 OpF VCC‘o/Z (z -> L) 1M0 oo OpF v ‘0/2 .5 IIO (H -> Z) so 100 OpF v0 .5 IIO (L -> Z) 100 00 OpF Output test Condllians tor an other mlerfaces are determined by the respecﬂve s‘anda

3-55

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

Switching Test Conditions

Figure 3-26 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,

voltage, and other test conditions are shown in Table 3-23.

Figure 3-26. Output Test Load, LVTTL and LVCMOS Standards

Table 3-23. Test Fixture Required Components, Non-Terminated Interfaces

Test Condition R1R2CLTiming Ref. VT

LVTTL and other LVCMOS settings (L -> H, H -> L) 

0pF

LVCMOS 3.3 = 1.5V —

LVCMOS 2.5 = VCCIO/2 —

LVCMOS 1.8 = VCCIO/2 —

LVCMOS 1.5 = VCCIO/2 —

LVCMOS 1.2 = VCCIO/2 —

LVCMOS 2.5 I/O (Z -> H) 1M0pF VCCIO/2 —

LVCMOS 2.5 I/O (Z -> L) 1M0pF VCCIO/2 VCCIO

LVCMOS 2.5 I/O (H -> Z) 100 0pF VOH - 0.10 —

LVCMOS 2.5 I/O (L -> Z) 100 0pF VOL + 0.10 VCCIO

Note: Output test conditions for all other interfaces are determined by the respective standards.

DUT

CL*

Test Point

*CL Includes Test Fixture and Probe Capacitance

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

vcco =3,av RT RT 20 Receiver V Current Source Mini LVDS Over Recommended Operatin Parameter Symbol Description Zo Single-ended PCB trace \mpedance RT Differentxal termmahon veststance VOD Output votiage, diﬂerential, |VOP - VD V05 Output voltage, common mode Avon Change in V09, between H an AV”) Change in Vos‘ between VTHD Input vottage, dittereniia VCM input votlage, com TH, TF Output rise TODUTV Output clock

3-56

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

sysI/O Differential Electrical Characteristics

Transition Reduced LVDS (TRLVDS DC Specification)

Over Recommended Operating Conditions

Mini LVDS

Over Recommended Operating Conditions

Symbol Description Min. Nom. Max. Units

VCCO Driver supply voltage (+/- 5%) 3.14 3.3 3.47 V

VID Input differential voltage 150 1200 mV

VICM Input common mode voltage 3 3.265 V

VCCO Termination supply voltage 3.14 3.3 3.47 V

RTTermination resistance (off-chip) 45 50 55 Ohms

Note: LatticeECP3 only supports the TRLVDS receiver.

Parameter Symbol Description Min. Typ. Max. Units

ZOSingle-ended PCB trace impedance 30 50 75 ohms

RTDifferential termination resistance 50 100 150 ohms

VOD Output voltage, differential, |VOP - VOM|300—600mV

VOS Output voltage, common mode, |VOP + VOM|/2 1 1.2 1.4 V

VOD Change in VOD, between H and L — — 50 mV

VID Change in VOS, between H and L — — 50 mV

VTHD Input voltage, differential, |VINP - VINM|200—600mV

VCM Input voltage, common mode, |VINP + VINM|/2 0.3+(VTHD/2) — 2.1-(VTHD/2)

TR, TFOutput rise and fall times, 20% to 80% — — 550 ps

TODUTY Output clock duty cycle 40 — 60 %

Note: Data is for 6mA differential current drive. Other differential driver current options are available.

Current

Source

VCCO = 3.3V

RTRT

Transmitter

Receiver

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

peraling Con ons Min. Typ. Max. Units 0 ohms 100 200 600 mV 0.5 1.2 1.5 V currenl 1 2 6 mA 100 — — m Rage 0.3 — 1.5 Ixmes, 20% m 80% — 500 — Output clock duly cycle 35 5O 65 renua‘ dnver current ophons are avaname.

3-57

DC and Switching Characteristics

Lattice Semiconductor LatticeECP3 Family Data Sheet

Point-to-Point LVDS (PPLVDS)

Over Recommended Operating Conditions

RSDS

Over Recommended Operating Conditions

Description Min. Typ. Max. Units

Output driver supply (+/- 5%) 3.14 3.3 3.47 V

2.25 2.5 2.75 V

Input differential voltage 100 400 mV

Input common mode voltage 0.2 2.3 V

Output differential voltage 130 400 mV

Output common mode voltage 0.5 0.8 1.4 V

Parameter Symbol Description Min. Typ. Max. Units

VOD Output voltage, differential, RT = 100 ohms 100 200 600 mV

VOS Output voltage, common mode 0.5 1.2 1.5 V

IRSDS Differential driver output current 1 2 6 mA

VTHD Input voltage differential 100 — — mV

VCM Input common mode voltage 0.3 — 1.5 V

TR, TFOutput rise and fall times, 20% to 80% — 500 — ps

TODUTY Output clock duty cycle 35 50 65 %

Note: Data is for 2mA drive. Other differential driver current options are available.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

Lattice“ Semiconductor Corporation ‘ iption the deVice on which the pad is located. Valid eft), B (Bottom), Fl (Right). T (Top). ndicales the PFU row or the column of the device on isis. When Edge is T (Top) or B (Bottom), only need to spec- er. When Edge is l. (Left) or R (Right). only need to specify [A/B] indicates the PlD Within the PIC to which the pad is connected. Some ol r-programmaple pins are shared with special function pins. These ns. when not used as special purpose pins, can be programmed as l/Os for r logic. During conliguration the user-programmable l/Os are tri-staled with an internal pull-up resistor enabled If any pin is not used (or not bonded to a package pin). it is also tri-stated with an internal pull-up resistor ena after conliguration. These general purpose signals are input-only pins and are locat PLLS. Global RESET signal (active low). Any l/D pin can be GSR No connect. This pin is reserved and should not be connectedt Ground. Dedicated pins. Power supply pins for core logic. Dedicated p Auxiliary power supply pin. This dedicated pi referenced inpui butters. Dedicated power supply pins for l/O b SERDES, transmn. receive, PLL LL,[LOC] — General purpose PLL supply pin VREFLXI VREFLX — Relerence supply pins lo assigned as VHEF inp VTTX — Power supply for on-c 1.25Gbps). XFlES‘ — 10K ohm +/'1°/o PLL, DLL and Clock Functions [LOC][num],GPl_l_[T. CLlNJindex] i Gen from [LOC][num],GPl_l_[T, CLFBJindex] i [LOC]0,GDLLT,IN,[index] [LOC]0,GDLLT,FB,[index]

www.latticesemi.com 4-1 DS1021 Pinout Information_01.2

March 2010 Preliminary Data Sheet DS1021

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

Signal Descriptions

Signal Name I/O Description

General Purpose

P[Edge] [Row/Column Number]_[A/B] I/O

[Edge] indicates the edge of the device on which the pad is located. Valid

edge designations are L (Left), B (Bottom), R (Right), T (Top).

[Row/Column Number] indicates the PFU row or the column of the device on

which the PIC exists. When Edge is T (Top) or B (Bottom), only need to spec-

ify Column Number. When Edge is L (Left) or R (Right), only need to specify

Row Number.

[A/B] indicates the PIO within the PIC to which the pad is connected. Some of

these user-programmable pins are shared with special function pins. These

pins, when not used as special purpose pins, can be programmed as I/Os for

user logic. During configuration the user-programmable I/Os are tri-stated

with an internal pull-up resistor enabled. If any pin is not used (or not bonded

to a package pin), it is also tri-stated with an internal pull-up resistor enabled

after configuration.

P[Edge][Row Number]E_[A/B/C/D] I These general purpose signals are input-only pins and are located near the

PLLs.

GSRN I Global RESET signal (active low). Any I/O pin can be GSRN.

NC — No connect.

RESERVED — This pin is reserved and should not be connected to anything on the board.

GND — Ground. Dedicated pins.

VCC — Power supply pins for core logic. Dedicated pins.

VCCAUX —

Auxiliary power supply pin. This dedicated pin powers all the differential and

referenced input buffers.

VCCIOx — Dedicated power supply pins for I/O bank x.

VCCA — SERDES, transmit, receive, PLL and reference clock buffer power supply.

VCCPLL_[LOC] — General purpose PLL supply pins where LOC=L (left) or R (right).

VREF1_x, VREF2_x —Reference supply pins for I/O bank x. Pre-determined pins in each bank are

assigned as VREF inputs. When not used, they may be used as I/O pins.

VTTx — Power supply for on-chip termination of I/Os (Required for DDR3 and LVDS at

1.25Gbps).

XRES1— 10K ohm +/-1% resistor must be connected between this pad and ground.

PLL, DLL and Clock Functions

[LOC][num]_GPLL[T, C]_IN_[index] I General Purpose PLL (GPLL) input pads: LUM, LLM, RUM, RLM, num = row

from center, T = true and C = complement, index A,B,C...at each side.

[LOC][num]_GPLL[T, C]_FB_[index] I Optional feedback GPLL input pads: LUM, LLM, RUM, RLM, num = row from

center, T = true and C = complement, index A,B,C...at each side.

[LOC]0_GDLLT_IN_[index] I/O General Purpose DLL (GDLL) input pads where LOC=RUM or LUM, T is True

Complement, index is A or B.

[LOC]0_GDLLT_FB_[index] I/O Optional feedback GDLL input pads where LOC=RUM or LUM, T is True

Complement, index is A or B.

PCLK[T, C][n:0]_[3:0] I Primary Clock pads, T = true and C = complement, n per side, indexed by

bank and 0, 1, 2, 3 within bank.

LatticeECP3 Family Data Sheet

Pinout Information

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

om), I. (left), DQ. associated nlrol the 1149.1 state machine. Pull-up is n clock the 1149.1 state machine. No pull-up d to load data into devrce usrng 1149.1 state machine. is TAP port can be activated for configuration by sending command. (Note: once a conliguration port is selected it is conlrguration port cannot be selected until the power-up ). Pull-up is enabled during configuration. n. Test Data Out pin used to shift data out of a device using 1149.1. Power supply pin for JTAG Test Access Port. Mode pins used to specify configuration mode values latched on nsrn of INITN. During conlrguration, a pull-up is enabled. These are dedica pins Open Drain pin. Indicates the FPGA is ready to be configured. D V0 uration, a pull-up is enabled. It is a dedicated pin. I Initiates configuration sequence when asserted low This p active pull-up. It is a dedicated pin I/O Open Drain pin. Indicates that the configuration se the startup sequence is in progress. It is a dedicate I Input Conliguration Clock for configuring an CPU modes It is a dedicated pin. I/O Output Configuration Clock for configu ter configuration modes. SV/SISPI 0 Parallel conlrguration mode busy Parallel conlrguration mod ect. CSN/SN/OEN V0 Parallel burst Flash 0qu CS1 N/HOLDN/RDY I Parallel conliguration WFIITEN I Write enable for DOUT/CSON/CSSPH N 0 Serial data oulpu sysCONFI D[0]/SPIFASTN I/O SysCONFI mod drain D1 I/O D2 I/O DSISI D4/SO

4-2

Pinout Information

Lattice Semiconductor LatticeECP3 Family Data Sheet

[LOC]DQS[num] I/O DQ input/output pads: T (top), R (right), B (bottom), L (left), DQS, num = ball

function number.

[LOC]DQ[num] I/O DQ input/output pads: T (top), R (right), B (bottom), L (left), DQ, associated

DQS number.

Test and Programming (Dedicated Pins)

TMS I Test Mode Select input, used to control the 1149.1 state machine. Pull-up is

enabled during configuration.

TCK I

Test Clock input pin, used to clock the 1149.1 state machine. No pull-up

enabled.

TDI I

Test Data in pin. Used to load data into device using 1149.1 state machine.

After power-up, this TAP port can be activated for configuration by sending

appropriate command. (Note: once a configuration port is selected it is

locked. Another configuration port cannot be selected until the power-up

sequence). Pull-up is enabled during configuration.

TDO O Output pin. Test Data Out pin used to shift data out of a device using 1149.1.

VCCJ — Power supply pin for JTAG Test Access Port.

Configuration Pads (Used During sysCONFIG)

CFG[2:0] I

Mode pins used to specify configuration mode values latched on rising edge

of INITN. During configuration, a pull-up is enabled. These are dedicated

pins.

INITN I/O

Open Drain pin. Indicates the FPGA is ready to be configured. During config-

uration, a pull-up is enabled. It is a dedicated pin.

PROGRAMN I

Initiates configuration sequence when asserted low. This pin always has an

active pull-up. It is a dedicated pin.

DONE I/O

Open Drain pin. Indicates that the configuration sequence is complete, and

the startup sequence is in progress. It is a dedicated pin.

CCLK I Input Configuration Clock for configuring an FPGA in Slave SPI, Serial, and

CPU modes. It is a dedicated pin.

MCLK I/O Output Configuration Clock for configuring an FPGA in SPI, SPIm, and Mas-

ter configuration modes.

BUSY/SISPI O Parallel configuration mode busy indicator. SPI/SPIm mode data output.

CSN/SN/OEN I/O Parallel configuration mode active-low chip select. Slave SPI chip select. 

Parallel burst Flash output enable.

CS1N/HOLDN/RDY I Parallel configuration mode active-low chip select. Slave SPI hold input.

WRITEN I Write enable for parallel configuration modes.

DOUT/CSON/CSSPI1N O Serial data output. Chip select output. SPI/SPIm mode chip select.

D[0]/SPIFASTN I/O

sysCONFIG Port Data I/O for Parallel mode. Open drain during configuration.

sysCONFIG Port Data I/O for SPI or SPIm. When using the SPI or SPIm

mode, this pin should either be tied high or low, must not be left floating. Open

drain during configuration.

D1 I/O Parallel configuration I/O. Open drain during configuration.

D2 I/O Parallel configuration I/O. Open drain during configuration.

D3/SI I/O Parallel configuration I/O. Slave SPI data input. Open drain during configura-

tion.

D4/SO I/O Parallel configuration I/O. Slave SPI data output. Open drain during configura-

tion.

D5 I/O Parallel configuration I/O. Open drain during configuration.

D6/SPID1 I/O Parallel configuration I/O. SPI/SPIm data input. Open drain during configura-

tion.

Signal Descriptions (Cont.)

Signal Name I/O Description

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

m mode chip select nel m elm ock lnpul channel m ositive channel m Clock lnpul power supply, channel m (1 2V/1.5) buller power supply, channel m (l.2V/1.5V) aeslgneu m supply the devlce will the proper relerence or supply vollage,

4-3

Pinout Information

Lattice Semiconductor LatticeECP3 Family Data Sheet

D7/SPID0 I/O Parallel configuration I/O. SPI/SPIm data input. Open drain during configura-

tion.

DI/CSSPI0N/CEN I/O Serial data input for slave serial mode. SPI/SPIm mode chip select.

Dedicated SERDES Signals2

PCS[Index]_HDINNm I High-speed input, negative channel m

PCS[Index]_HDOUTNm O High-speed output, negative channel m

PCS[Index]_REFCLKN I Negative Reference Clock Input

PCS[Index]_HDINPm I High-speed input, positive channel m

PCS[Index]_HDOUTPm O High-speed output, positive channel m

PCS[Index]_REFCLKP I Positive Reference Clock Input

PCS[Index]_VCCOBm — Output buffer power supply, channel m (1.2V/1.5)

PCS[Index]_VCCIBm — Input buffer power supply, channel m (1.2V/1.5V)

1. When placing switching I/Os around these critical pins that are designed to supply the device with the proper reference or supply voltage,

care must be given.

2. m defines the associated channel in the quad.

Signal Descriptions (Cont.)

Signal Name I/O Description

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

DQ DQ DQ DO DQ [Edge]DQSn DQ DQ m DO )> Do m DO Devi ce DQ DQ DQ DO MPH] DO DQ Edge] [n1 [Edge] DQSn DQ P[Edge] [n+1] DQ P[Edge] [n+2] m>m>m>m>m>m> N019. “n" \s a row PIC number

4-4

Pinout Information

Lattice Semiconductor LatticeECP3 Family Data Sheet

PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin

PICs Associated with

DQS Strobe PIO Within PIC

DDR Strobe (DQS) and

Data (DQ) Pins

For Left and Right Edges of the Device

P[Edge] [n-3] ADQ

BDQ

P[Edge] [n-2] ADQ

BDQ

P[Edge] [n-1] ADQ

BDQ

P[Edge] [n] A[Edge]DQSn

BDQ

P[Edge] [n+1] ADQ

BDQ

P[Edge] [n+2] ADQ

BDQ

For Top Edge of the Device

P[Edge] [n-3] ADQ

BDQ

P[Edge] [n-2] ADQ

BDQ

P[Edge] [n-1] ADQ

BDQ

P[Edge] [n] A [Edge]DQSn

BDQ

P[Edge] [n+1] ADQ

BDQ

P[Edge] [n+2] ADQ

BDQ

Note: “n” is a row PIC number.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

D a s U .0 e d n E VCCPLL TAP GND, GNDIO

4-5

Pinout Information

Lattice Semiconductor LatticeECP3 Family Data Sheet

Pin Information Summary

Pin Information Summary ECP3-17EA ECP3-35EA ECP3-70E/EA

Pin Type

256

ftBGA

484

fpBGA

256

ftBGA

484

fpBGA

672

fpBGA

484

fpBGA

672

fpBGA

1156

fpBGA

General Purpose

Inputs/Outputs per Bank

Bank 0 2636264248426086

Bank 1 1424143636364878

Bank 2 6 12 6 2424243436

Bank 3 1844165459545986

Bank 6 2044186361636786

Bank 7 1932193642364854

Bank 8 2424242424242424

General Purpose Inputs per

Bank

Bank 0 00000000

Bank 1 00000000

Bank 2 22244488

Bank 3 0024441212

Bank 6 0024441212

Bank 7 44444488

Bank 8 00000000

General Purpose Outputs per

Bank

Bank 0 00000000

Bank 1 00000000

Bank 2 00000000

Bank 3 00000000

Bank 6 00000000

Bank 7 00000000

Bank 8 00000000

Total Single-Ended User I/O 133 222 133 295 310 295 380 490

VCC 6 16 6 1632163232

VCCAUX 48481281216

VTT 44444448

VCCA 444484816

VCCPLL 24244444

VCCIO

Bank 0 22224244

Bank 1 22224244

Bank 2 22224244

Bank 3 22224244

Bank 6 22224244

Bank 7 22224244

Bank 8 22222222

VCCJ 11111111

TAP 44444444

GND, GNDIO 50 98 50 98 139 98 139 233

NC 0730 0960 0238

Reserved102022222

SERDES 2626262626265278

Miscellaneous Pins 88888888

Total Bonded Pins 256 484 256 484 672 484 672 1156

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

21 24 18 18 1 8 8 5 20 19 6 22 20 6 1 1 13 12 12 12 12 0 0 0 0 0 0 0 U 3 3 6 6 5 9 4 9 12 5 9 4 1 1 12 5 8 5 9 10 0 0 0 0 0 26/13 36/18 26/13 42/21 14/7 24/12 14/7 36/18 8/4 14/7 8/4 28/14 k 3 18/9 44/22 18/9 58/2 Bank 6 20/10 44/22 20/10 67/3 Bank 7 23/11 36/18 23/11 Bank 8 24/12 24/12 24/12 Bank 0 2 3 2 Bank 1 1 2 1 Bank 2 0 1 ups Bonded per Bank 3 1 3 Bank 6 1 3 Bank 7 1 Configurahon Bank 8 0 SERDES Quads 1 1. These pms mus1remamfloa1mg on me board

4-6

Pinout Information

Lattice Semiconductor LatticeECP3 Family Data Sheet

Pin Information Summary (Cont.)

Pin Information Summary ECP3-17EA ECP3-35EA

Pin Type 256 ftBGA 484 fpBGA 256 ftBGA 484 fpBGA 672 fpBGA

Emulated Differential I/O per

Bank

Bank 0 1318132124

Bank 1 7 12 7 18 18

Bank 2 24188

Bank 3 4 13 5 20 19

Bank 6 5 13 6 22 20

Bank 7 6 10 6 11 13

Bank 8 1212121212

Highspeed Differential I/O per

Bank

Bank 0 00000

Bank 1 00000

Bank 2 23366

Bank 3 594912

Bank 6 5 9 4 11 12

Bank 7 585910

Bank 8 00000

Total Single Ended/ Total

Differential I/O per Bank

Bank 0 26/13 36/18 26/13 42/21 48/24

Bank 1 14/7 24/12 14/7 36/18 36/18

Bank 2 8/4 14/7 8/4 28/14 28/14

Bank 3 18/9 44/22 18/9 58/29 63/31

Bank 6 20/10 44/22 20/10 67/33 65/32

Bank 7 23/11 36/18 23/11 40/20 46/23

Bank 8 24/12 24/12 24/12 24/12 24/12

DDR Groups Bonded per

Bank

Bank 0 23234

Bank 1 12133

Bank 2 01022

Bank 3 13134

Bank 6 13144

Bank 7 12133

Configuration Bank 800000

SERDES Quads 11111

1. These pins must remain floating on the board.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

30 43 18 24 39 8 12 13 20 23 33 39 22 25 33 22 11 16 18 12 12 12 12 0 0 0 0 0 0 0 0 0 0 6 6 6 9 9 8 10 9 12 16 7 9 10 11 14 16 6 8 9 9 12 1 0 0 0 0 0 42/21 60/30 86/43 42/21 60/30 36/18 48/24 78/39 36/18 48/24 28/14 42/21 44/22 28/14 42 ank 3 58/29 71/35 98/49 58/29 71 ank 6 67/33 79/38 98/49 67/33 Bank 7 40/20 56/28 62/31 40/20 Bank 8 24/12 24/12 24/12 24 Bank 0 3 5 7 Bank 1 3 A 7 Bank 2 2 3 3 BaGanups Bonded Bank 3 3 A 5 Bank 6 4 A Bank 7 3 A Conligurauon Bank 8 0 0 SERDES Quads 1

4-7

Pinout Information

Lattice Semiconductor LatticeECP3 Family Data Sheet

Pin Information Summary (Cont.)

Pin Information Summary ECP3-70E ECP3-70EA

Pin Type 484 fpBGA 672 fpBGA

1156

fpBGA 484 fpBGA 672 fpBGA

1156

fpBGA

Emulated Differential 

I/O per Bank

Bank 0 213043213043

Bank 1 182439182439

Bank 2 101516 8 1213

Bank 3 232739202333

Bank 6 263039222533

Bank 7 142022111618

Bank 8 121212121212

High-Speed Differential

I/O per Bank

Bank 0 000000

Bank 1 000000

Bank 2 466699

Bank 3 6 81091216

Bank 6 7 9 10111416

Bank 7 68991213

Bank 8 000000

Total Single-Ended/

Total Differential I/O

per Bank

Bank 0 42/21 60/30 86/43 42/21 60/30 86/43

Bank 1 36/18 48/24 78/39 36/18 48/24 78/39

Bank 2 28/14 42/21 44/22 28/14 42/21 44/22

Bank 3 58/29 71/35 98/49 58/29 71/35 98/49

Bank 6 67/33 79/38 98/49 67/33 78/39 98/49

Bank 7 40/20 56/28 62/31 40/20 56/28 62/31

Bank 8 24/12 24/12 24/12 24/12 24/12 24/12

DDR Groups Bonded

per Bank

Bank 0 357357

Bank 1 347347

Bank 2 233233

Bank 3 345345

Bank 6 445445

Bank 7 344344

Configuration Bank 8000000

SERDES Quads 123123

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

m z: 1; on m m m a (non mm mm \ILO w b 1; on N 4; m a m a moo coco moo mm mm mm oooooooom ccooooccm oooooam Ended User HO 0 mmmbbbm VCC‘O VCCJ TAP GND, GNDIO NC Reserved

4-8

Pinout Information

Lattice Semiconductor LatticeECP3 Family Data Sheet

Pin Information Summary (Cont.)

Pin Information Summary ECP3-95E/EA ECP3-150EA

Pin Type

484

fpBGA

672

fpBGA

1156

fpBGA

672

fpBGA

1156

fpBGA

General Purpose

Inputs/Outputs per bank

Bank 0 4260866094

Bank 1 3648784886

Bank 2 2434363458

Bank 3 54598659104

Bank 6 63678667104

Bank 7 3648544876

Bank 8 2424242424

General Purpose Inputs per

Bank

Bank 0 00000

Bank 1 00000

Bank 2 48888

Bank 3 4 12 12 12 12

Bank 6 4 12 12 12 12

Bank 7 48888

Bank 8 00000

General Purpose Outputs per

Bank

Bank 0 00000

Bank 1 00000

Bank 2 00000

Bank 3 00000

Bank 6 00000

Bank 7 00000

Bank 8 00000

Total Single-Ended User I/O 295 380 490 380 586

VCC 1632323232

VCCAUX 8 12161216

VTT 44848

VCCA 4 8 16 8 16

VCCPLL 44444

VCCIO

Bank 0 24444

Bank 1 24444

Bank 2 24444

Bank 3 24444

Bank 6 24444

Bank 7 24444

Bank 8 22222

VCCJ 11111

TAP 44444

GND, GNDIO 98 139 233 139 233

NC 0 0 238 0 116

Reserved122222

SERDES 26527852104

Miscellaneous Pins 88888

Total Bonded Pins 484 672 1156 672 1156

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

43 30 47 39 24 43 1 2 1 3 1 2 1 8 23 33 23 37 25 33 25 37 1 1 1 6 1 8 1 6 24 1 2 1 2 1 2 1 2 1 2 0 0 0 0 0 0 0 0 0 0 6 6 9 9 9 1 5 1 0 9 1 2 1 6 12 21 9 1 0 1 1 1 4 1 6 1 4 21 8 9 9 1 2 1 3 12 0 0 0 0 0 0 42/21 60/30 86/43 42/21 60/30 86/43 60/30 36/18 48/24 78/39 36/18 48/24 78/39 48/24 28/14 42/21 44/22 28/14 42/21 44/22 58/29 71/35 98/49 58/29 71/35 98/49 67/33 78/39 98/49 67/33 78/39 98/ n k 7 40/20 56/28 62/31 40/20 56/28 62/ Banks 24/12 24/12 24/12 24/12 24/12 Bank 0 3 5 7 3 5 Bank 1 3 4 7 3 Bank 2 2 3 3 2 deedmups Bank 3 3 4 5 a Bank Bank 6 4 4 5 4 Bank 7 3 4 4 ggxgurauon 0 0 0 S E R D ES Quads 1 2 3 LThese pms must remam ﬂoatmg on me board.

4-9

Pinout Information

Lattice Semiconductor LatticeECP3 Family Data Sheet

Pin Information Summary (Cont.)

Pin Information Summary ECP3-95E ECP3-95EA ECP3-150EA

Pin Type

484

fpBGA

672

fpBGA

1156

fpBGA

484

fpBGA

672

fpBGA

1156

fpBGA

672

fpBGA

1156

fpBGA

Emulated

Differential I/O 

per Bank

Bank 0 213043 21 30 43 3047

Bank 1 182439 18 24 39 2443

Bank 2 10 15 16 8 12 13 12 18

Bank 3 232739 20 23 33 2337

Bank 6 263039 22 25 33 2537

Bank 7 142022 11 16 18 1624

Bank 8 121212 12 12 12 1212

Highspeed

Differential I/O 

per Bank

Bank 0 000 0 0 0 00

Bank 1 000 0 0 0 00

Bank 2 4 6 6 6 9 9 9 15

Bank 3 6 8 10 9 12 16 12 21

Bank 6 79101114161421

Bank 7 689 9 12131218

Bank 8 000 0 0 0 00

Total Single Ended/

Total Differential

I/O per Bank

Bank 0 42/21 60/30 86/43 42/21 60/30 86/43 60/30 94/47

Bank 1 36/18 48/24 78/39 36/18 48/24 78/39 48/24 86/43

Bank 2 28/14 42/21 44/22 28/14 42/21 44/22 42/21 66/33

Bank 3 58/29 71/35 98/49 58/29 71/35 98/49 71/35 116/58

Bank 6 67/33 78/39 98/49 67/33 78/39 98/49 78/39 116/58

Bank 7 40/20 56/28 62/31 40/20 56/28 62/31 56/28 84/42

Bank 8 24/12 24/12 24/12 24/12 24/12 24/12 24/12 24/12

DDR Groups

Bonded 

per Bank

Bank 0 357 3 5 7 57

Bank 1 347 3 4 7 47

Bank 2 233 2 3 3 34

Bank 3 345 3 4 5 47

Bank 6 445 4 4 5 47

Bank 7 344 3 4 4 46

Configuration

Bank8 000 0 0 0 00

SERDES Quads 1 2 3 1 2 3 2 4

1.These pins must remain floating on the board.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

www.larlicesemi.com/groducts/fgga/ecgs gn methodology. To assess the thermal nction temperature in all device data sheets. 0 ensure that the device and package do not agement document to find the device/package ent, refer to the lollowing: Thermal Management Power Consuthion and Manauemenl for LatticeECP3 Devices attice ispLEVEFl de5ign tool, or as a standalone download from www.larlicesemicom/software

4-10

Pinout Information

Lattice Semiconductor LatticeECP3 Family Data Sheet

Logic Signal Connections

Package pinout information can be found under “Data Sheets” on the LatticeECP3 product pages on the Lattice

website at www.latticesemi.com/products/fpga/ecp3 and in the Lattice ispLEVER Design Planner software. To cre-

ate pinout information from within Design Planner, select View -> Package View. Then select Select File ->

Export and choose a type of output file. See Design Planner help for more information.

Thermal Management

Thermal management is recommended as part of any sound FPGA design methodology. To assess the thermal

characteristics of a system, Lattice specifies a maximum allowable junction temperature in all device data sheets.

Designers must complete a thermal analysis of their specific design to ensure that the device and package do not

exceed the junction temperature limits. Refer to the Thermal Management document to find the device/package

specific thermal values.

For Further Information

For further information regarding Thermal Management, refer to the following:

•Thermal Management document

• TN1181, Power Consumption and Management for LatticeECP3 Devices

• Power Calculator tool included with the Lattice ispLEVER design tool, or as a standalone download from 

www.latticesemi.com/software

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

Lattice“ ' Semiconguctor Corporation Q 1 e C : Commevmal I: \nduslvial Package FTN256 = 256-133“ Lead-Frae “BGA FN484 = 484-ball Lead-Flea prGA FN672 : 672-ball Lead-Flea prGA FN1156 :1156-baHLead-FraelpBGA xoprside markings, for commercial and indusmal grades, as shown he Commerclal Induslrlal Lattice Ech LFESVQSE 7FN6720 Datecade LFEBVQS E 7FN672\ Datecode

www.latticesemi.com 5-1 DS1021 Order Info_01.2

March 2010 Preliminary Data Sheet DS1021

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

LatticeECP3 Part Number Description

LFE3 – XXX XX – X XXXXXX X

Grade

C = Commercial

I = Industrial

Logic Capacity

17 = 17K LUTs

35 = 33K LUTs

70 = 67K LUTs

95 = 92K LUTs

150 = 149K LUTs

Supply Voltage

E or EA = 1.2V

Speed

6 = Slowest

8 = Fastest

Package

FTN256 = 256-ball Lead-Free ftBGA

FN484 = 484-ball Lead-Free fpBGA

FN672 = 672-ball Lead-Free fpBGA

FN1156 = 1156-ball Lead-Free fpBGA

Device Family

ECP3 (LatticeECP3 FPGA + SERDES)

Ordering Information

LatticeECP3 devices have top-side markings, for commercial and industrial grades, as shown below:

LFE3-95E

7FN672C

Datecode

ECP3

LFE3-95E

7FN672I

Datecode

Commercial Industrial

ECP3

LatticeECP3 Family Data Sheet

Ordering Information

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

Temp. LUTs (K) 256 COM 17 256 COM 17 256 COM 17 484 COM 17 lpBGA 484 COM 17 lpBGA 484 COM 17 Package Pins Temp. LUTs (K) Lead-Free ﬂBGA 256 COM 33 Lead-Free RBGA 256 COM 33 -8 Lead-Free RBGA 256 COM -6 Lead-Free lpBGA 484 COM -7 Lead-Free prGA 484 COM -a Lead-Free prGA 484 COM 2V -6 Lead-Free lpBGA 672 COM 1 2V -7 Lead-Free lpBGA 672 COM 1 2V -8 Lead-Free lpBGA 672 Number Voltage Grade Package P DEA-GFNABAC 1 2V -6 Lead-Free prGA -70EA-7FN484C 1 2V -7 Lead-Free lpBGA -70EA-8FN484C 1.2V -8 Lead-Free lpBG LFE3-70EA-6FN6720 1.2V -6 Lead-Free LFE3-70EA-7FN672C 1 2V -7 Lead-Free LFE3-70EA-8FN672C 1.2V -8 Lead LFE3-70EA-6FN1156C 1 2V -6 Lead LFE3-70EA-7FN1156C 1 2V -7 LFE3-70EA-8FN1156C 1.2V -8

5-2

Ordering Information

Lattice Semiconductor LatticeECP3 Family Data Sheet

LatticeECP3 Devices, Lead-Free Packaging

The following devices may have associated errata. Specific devices with associated errata will be notated with a

footnote.

Commercial

Part Number Voltage Grade Package Pins Temp. LUTs (K)

LFE3-17EA-6FTN256C 1.2V -6 Lead-Free ftBGA 256 COM 17

LFE3-17EA-7FTN256C 1.2V -7 Lead-Free ftBGA 256 COM 17

LFE3-17EA-8FTN256C 1.2V -8 Lead-Free ftBGA 256 COM 17

LFE3-17EA-6FN484C 1.2V -6 Lead-Free fpBGA 484 COM 17

LFE3-17EA-7FN484C 1.2V -7 Lead-Free fpBGA 484 COM 17

LFE3-17EA-8FN484C 1.2V -8 Lead-Free fpBGA 484 COM 17

Part Number Voltage Grade Package Pins Temp. LUTs (K)

LFE3-35EA-6FTN256C 1.2V -6 Lead-Free ftBGA 256 COM 33

LFE3-35EA-7FTN256C 1.2V -7 Lead-Free ftBGA 256 COM 33

LFE3-35EA-8FTN256C 1.2V -8 Lead-Free ftBGA 256 COM 33

LFE3-35EA-6FN484C 1.2V -6 Lead-Free fpBGA 484 COM 33

LFE3-35EA-7FN484C 1.2V -7 Lead-Free fpBGA 484 COM 33

LFE3-35EA-8FN484C 1.2V -8 Lead-Free fpBGA 484 COM 33

LFE3-35EA-6FN672C 1.2V -6 Lead-Free fpBGA 672 COM 33

LFE3-35EA-7FN672C 1.2V -7 Lead-Free fpBGA 672 COM 33

LFE3-35EA-8FN672C 1.2V -8 Lead-Free fpBGA 672 COM 33

Part Number Voltage Grade Package Pins Temp. LUTs (K)

LFE3-70EA-6FN484C 1.2V -6 Lead-Free fpBGA 484 COM 67

LFE3-70EA-7FN484C 1.2V -7 Lead-Free fpBGA 484 COM 67

LFE3-70EA-8FN484C 1.2V -8 Lead-Free fpBGA 484 COM 67

LFE3-70EA-6FN672C 1.2V -6 Lead-Free fpBGA 672 COM 67

LFE3-70EA-7FN672C 1.2V -7 Lead-Free fpBGA 672 COM 67

LFE3-70EA-8FN672C 1.2V -8 Lead-Free fpBGA 672 COM 67

LFE3-70EA-6FN1156C 1.2V -6 Lead-Free fpBGA 1156 COM 67

LFE3-70EA-7FN1156C 1.2V -7 Lead-Free fpBGA 1156 COM 67

LFE3-70EA-8FN1156C 1.2V -8 Lead-Free fpBGA 1156 COM 67

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

COM COM 672 COM 672 COM 1 156 COM 1 156 COM lpBGA 1156 COM wwaamcesem,com/documems/ds1021,1IQlor a descnplion of me errata. Package Pins Temp. LUTs (K) Lead-Free prGA 484 COM 92 Lead-Free lpBGA 484 COM 92 -8 Lead-Free lpBGA 484 COM 92 -6 Lead-Free lpBGA 672 COM -7 Lead-Free lpBGA 672 COM -8 Lead-Free lpBGA 672 COM -6 Lead-Free prGA 1156 COM 1 2V -7 Lead-Free IpBGA 1156 COM 1 2V -8 Lead-Free lpBGA 1156 Number Voltage Grade Package Pins 5E-6FN484C‘ 1 2V -6 Lead-Free prGA 4 5E-7FN484C‘ 1 2V -7 Lead-Free prGA -95E-8FN4B4C‘ 1 2V -8 Lead-Free lpBGA -95E-6FN67201 1.2V -6 Lead-Free lpBG LFEB-QSE-7FN672C‘ 1.2V -7 Lead-Free 1p LFEB-QSE-BFN672C‘ 1 2V -8 Lead-Free LFEB-QSE-GFN1 156C‘ 1.2V -6 Lead LFEB-QSE-7FN1156C‘ 1 2V -7 Lead LFEB-QSE-BFNHSGC‘ 1 2V -8 1.This devxce has assocxaled errata. View wwaamcesem,com/documems/ds1021,zug Part Number Voltage LFE3-150EA-6FN6720 1.2V LFE3-150EA-7FN672C 1.2 LFE3-150EA-8FN672C 1.2

5-3

Ordering Information

Lattice Semiconductor LatticeECP3 Family Data Sheet

Part Number Voltage Grade Package Pins Temp. LUTs (K)

LFE3-70E-6FN484C11.2V -6 Lead-Free fpBGA 484 COM 67

LFE3-70E-7FN484C11.2V -7 Lead-Free fpBGA 484 COM 67

LFE3-70E-8FN484C11.2V -8 Lead-Free fpBGA 484 COM 67

LFE3-70E-6FN672C11.2V -6 Lead-Free fpBGA 672 COM 67

LFE3-70E-7FN672C11.2V -7 Lead-Free fpBGA 672 COM 67

LFE3-70E-8FN672C11.2V -8 Lead-Free fpBGA 672 COM 67

LFE3-70E-6FN1156C11.2V -6 Lead-Free fpBGA 1156 COM 67

LFE3-70E-7FN1156C11.2V -7 Lead-Free fpBGA 1156 COM 67

LFE3-70E-8FN1156C11.2V -8 Lead-Free fpBGA 1156 COM 67

1.This device has associated errata. View www.latticesemi.com/documents/ds1021.zip for a description of the errata.

Part Number Voltage Grade Package Pins Temp. LUTs (K)

LFE3-95EA-6FN484C 1.2V -6 Lead-Free fpBGA 484 COM 92

LFE3-95EA-7FN484C 1.2V -7 Lead-Free fpBGA 484 COM 92

LFE3-95EA-8FN484C 1.2V -8 Lead-Free fpBGA 484 COM 92

LFE3-95EA-6FN672C 1.2V -6 Lead-Free fpBGA 672 COM 92

LFE3-95EA-7FN672C 1.2V -7 Lead-Free fpBGA 672 COM 92

LFE3-95EA-8FN672C 1.2V -8 Lead-Free fpBGA 672 COM 92

LFE3-95EA-6FN1156C 1.2V -6 Lead-Free fpBGA 1156 COM 92

LFE3-95EA-7FN1156C 1.2V -7 Lead-Free fpBGA 1156 COM 92

LFE3-95EA-8FN1156C 1.2V -8 Lead-Free fpBGA 1156 COM 92

Part Number Voltage Grade Package Pins Temp. LUTs (K)

LFE3-95E-6FN484C11.2V -6 Lead-Free fpBGA 484 COM 92

LFE3-95E-7FN484C11.2V -7 Lead-Free fpBGA 484 COM 92

LFE3-95E-8FN484C11.2V -8 Lead-Free fpBGA 484 COM 92

LFE3-95E-6FN672C11.2V -6 Lead-Free fpBGA 672 COM 92

LFE3-95E-7FN672C11.2V -7 Lead-Free fpBGA 672 COM 92

LFE3-95E-8FN672C11.2V -8 Lead-Free fpBGA 672 COM 92

LFE3-95E-6FN1156C11.2V -6 Lead-Free fpBGA 1156 COM 92

LFE3-95E-7FN1156C11.2V -7 Lead-Free fpBGA 1156 COM 92

LFE3-95E-8FN1156C11.2V -8 Lead-Free fpBGA 1156 COM 92

1.This device has associated errata. View www.latticesemi.com/documents/ds1021.zip for a description of the errata.

Part Number Voltage Grade Package Pins Temp. LUTs (K)

LFE3-150EA-6FN672C 1.2V -6 Lead-Free fpBGA 672 COM 149

LFE3-150EA-7FN672C 1.2V -7 Lead-Free fpBGA 672 COM 149

LFE3-150EA-8FN672C 1.2V -8 Lead-Free fpBGA 672 COM 149

LFE3-150EA-6FN1156C 1.2V -6 Lead-Free fpBGA 1156 COM 149

LFE3-150EA-7FN1156C 1.2V -7 Lead-Free fpBGA 1156 COM 149

LFE3-150EA-8FN1156C 1.2V -8 Lead-Free fpBGA 1156 COM 149

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

COM 149 COM 149 1156 COM 149 1156 COM 149 e IpBGA 1156 COM 149 SOEA-spFNpkgTW dewces, (where sp is the speed and d LFE3-150EA-spFNpkgl devxces respecﬁvely‘ except as hard PCS in me TW device 15 ml lunclxona‘ but it can be CDM Ieslmg al 250V.

5-4

Ordering Information

Lattice Semiconductor LatticeECP3 Family Data Sheet

Part Number Voltage Grade Package Pins Temp. LUTs (K)

LFE3-150EA-6FN672CTW* 1.2V -6 Lead-Free fpBGA 672 COM 149

LFE3-150EA-7FN672CTW* 1.2V -7 Lead-Free fpBGA 672 COM 149

LFE3-150EA-8FN672CTW* 1.2V -8 Lead-Free fpBGA 672 COM 149

LFE3-150EA-6FN1156CTW* 1.2V -6 Lead-Free fpBGA 1156 COM 149

LFE3-150EA-7FN1156CTW* 1.2V -7 Lead-Free fpBGA 1156 COM 149

LFE3-150EA-8FN1156CTW* 1.2V -8 Lead-Free fpBGA 1156 COM 149

*Note: Specifications for the LFE3-150EA-spFNpkgCTW and LFE3-150EA-spFNpkgITW devices, (where sp is the speed and

pkg is the package), are the same as the LFE3-150EA-spFNpkgC and LFE3-150EA-spFNpkgI devices respectively, except as

specified below.

• The CTC (Clock Tolerance Circuit) inside the SERDES hard PCS in the TW device is not functional but it can be

bypassed and implemented in soft IP.

• The SERDES XRES pin on the TW device passes CDM testing at 250V.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

Temp. IND IND IND IND IND IND LUTs(K) 17 17 17 17 17 17 Package Pins Temp. LUTs (K) Lead-Free IIBGA 256 IND 33 Lead-Free HBGA 256 IND 33 Lead-Free IIBGA 256 IND 33 -6 Lead-Free IpBGA 484 IND 33 -7 Lead-Free prGA 484 IND -8 Lead-Free prGA 484 IND -s Lead-Free prGA 672 IND 2V -7 Lead—Free prGA 672 IND 1 2V -7 Lead-Free prGA 672 IND Number Voltage Grade Package Pins 0EA-6FN484I 1.2V -6 Lead-Free prGA 4 0EA-7FN484I 1 2V -7 Lead-Free prGA 4 -70EA-8FN4B4I 1 2V -8 Lead-Free prGA -70EA-6FN672I 1 2V -6 Lead-Free prG LFE3-70EA-7FN672I 1.2V -7 Lead-Free fp LFE3-70EA-8FN672I 1 2V -8 Lead-Free LFE3-70EA-6FN1156I 1.2V -6 Lead LFE3-70EA-7FN1156I 1.2V -7 Lead LFE3-70EA-8FN1156I 1 2V -8

5-5

Ordering Information

Lattice Semiconductor LatticeECP3 Family Data Sheet

Industrial

The following devices may have associated errata. Specific devices with associated errata will be notated with a

footnote.

Part Number Voltage Grade Package Pins Temp. LUTs (K)

LFE3-17EA-6FTN256I 1.2V -6 Lead-Free ftBGA 256 IND 17

LFE3-17EA-7FTN256I 1.2V -7 Lead-Free ftBGA 256 IND 17

LFE3-17EA-8FTN256I 1.2V -8 Lead-Free ftBGA 256 IND 17

LFE3-17EA-6FN484I 1.2V -6 Lead-Free fpBGA 484 IND 17

LFE3-17EA-7FN484I 1.2V -7 Lead-Free fpBGA 484 IND 17

LFE3-17EA-8FN484I 1.2V -8 Lead-Free fpBGA 484 IND 17

Part Number Voltage Grade Package Pins Temp. LUTs (K)

LFE3-35EA-6FTN256I 1.2V -6 Lead-Free ftBGA 256 IND 33

LFE3-35EA-7FTN256I 1.2V -7 Lead-Free ftBGA 256 IND 33

LFE3-35EA-8FTN256I 1.2V -8 Lead-Free ftBGA 256 IND 33

LFE3-35EA-6FN484I 1.2V -6 Lead-Free fpBGA 484 IND 33

LFE3-35EA-7FN484I 1.2V -7 Lead-Free fpBGA 484 IND 33

LFE3-35EA-8FN484I 1.2V -8 Lead-Free fpBGA 484 IND 33

LFE3-35EA-6FN672I 1.2V -6 Lead-Free fpBGA 672 IND 33

LFE3-35EA-7FN672I 1.2V -7 Lead-Free fpBGA 672 IND 33

LFE3-35EA-8FN672I 1.2V -7 Lead-Free fpBGA 672 IND 33

Part Number Voltage Grade Package Pins Temp. LUTs (K)

LFE3-70EA-6FN484I 1.2V -6 Lead-Free fpBGA 484 IND 67

LFE3-70EA-7FN484I 1.2V -7 Lead-Free fpBGA 484 IND 67

LFE3-70EA-8FN484I 1.2V -8 Lead-Free fpBGA 484 IND 67

LFE3-70EA-6FN672I 1.2V -6 Lead-Free fpBGA 672 IND 67

LFE3-70EA-7FN672I 1.2V -7 Lead-Free fpBGA 672 IND 67

LFE3-70EA-8FN672I 1.2V -8 Lead-Free fpBGA 672 IND 67

LFE3-70EA-6FN1156I 1.2V -6 Lead-Free fpBGA 1156 IND 67

LFE3-70EA-7FN1156I 1.2V -7 Lead-Free fpBGA 1156 IND 67

LFE3-70EA-8FN1156I 1.2V -8 Lead-Free fpBGA 1156 IND 67

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

IND IND 672 IND 672 IND 672 IND 1 156 IND GA 1 156 IND IpBGA 1156 IND wwaaIIIcesemI,com/documenIs/ds1021,1IQ Ior a descnplion of Ihe errata. ade Package Pins Temp. LUTs (K) Lead-Free IpBGA 484 IND 92 -7 Lead-Free IpBGA 484 IND 92 -8 Lead-Free IpBGA 484 IND -6 Lead-Free IpBGA 672 IND -7 Lead-Free IpBGA 672 IND .2V -a Lead-Free prGA 672 IND 1 2V -6 Lead-Free prGA 1156 IND 1 2V -7 Lead-Free IpBGA 1156 1 2V -8 Lead-Free IpBGA 1156 Number Voltage Grade Package P -95E-6FN484II 1 2V -6 Lead-Free IpBGA -95E-7FN4B4II 1 2V -7 Lead-Free IpBG LFEB-QSE-BFNABAI‘ 1.2V -8 Lead-Free Ip LFEB-QSE-SFN672II 1 2V -6 Lead-Free LFEB-QSE-7FN672I‘ 1.2V -7 Lead LFEB-QSE-BFN672I‘ 1 2V -8 Lead LFEB-QSE-GFNHSGII 1 2V -6 LFEB-QSE-7FN1156I‘ 1.2V -7 LFEB-QSE-BFN1156I‘ 1.2V -8 1.This devxce has assocxaIed errata. View wwaaIIIcesemI,com/documenIs/ds1021,1IQ

5-6

Ordering Information

Lattice Semiconductor LatticeECP3 Family Data Sheet

Part Number Voltage Grade Package Pins Temp. LUTs (K)

LFE3-70E-6FN484I11.2V -6 Lead-Free fpBGA 484 IND 67

LFE3-70E-7FN484I11.2V -7 Lead-Free fpBGA 484 IND 67

LFE3-70E-8FN484I11.2V -8 Lead-Free fpBGA 484 IND 67

LFE3-70E-6FN672I11.2V -6 Lead-Free fpBGA 672 IND 67

LFE3-70E-7FN672I11.2V -7 Lead-Free fpBGA 672 IND 67

LFE3-70E-8FN672I11.2V -8 Lead-Free fpBGA 672 IND 67

LFE3-70E-6FN1156I11.2V -6 Lead-Free fpBGA 1156 IND 67

LFE3-70E-7FN1156I11.2V -7 Lead-Free fpBGA 1156 IND 67

LFE3-70E-8FN1156I11.2V -8 Lead-Free fpBGA 1156 IND 67

1.This device has associated errata. View www.latticesemi.com/documents/ds1021.zip for a description of the errata.

Part Number Voltage Grade Package Pins Temp. LUTs (K)

LFE3-95EA-6FN484I 1.2V -6 Lead-Free fpBGA 484 IND 92

LFE3-95EA-7FN484I 1.2V -7 Lead-Free fpBGA 484 IND 92

LFE3-95EA-8FN484I 1.2V -8 Lead-Free fpBGA 484 IND 92

LFE3-95EA-6FN672I 1.2V -6 Lead-Free fpBGA 672 IND 92

LFE3-95EA-7FN672I 1.2V -7 Lead-Free fpBGA 672 IND 92

LFE3-95EA-8FN672I 1.2V -8 Lead-Free fpBGA 672 IND 92

LFE3-95EA-6FN1156I 1.2V -6 Lead-Free fpBGA 1156 IND 92

LFE3-95EA-7FN1156I 1.2V -7 Lead-Free fpBGA 1156 IND 92

LFE3-95EA-8FN1156I 1.2V -8 Lead-Free fpBGA 1156 IND 92

Part Number Voltage Grade Package Pins Temp. LUTs (K)

LFE3-95E-6FN484I11.2V -6 Lead-Free fpBGA 484 IND 92

LFE3-95E-7FN484I11.2V -7 Lead-Free fpBGA 484 IND 92

LFE3-95E-8FN484I11.2V -8 Lead-Free fpBGA 484 IND 92

LFE3-95E-6FN672I11.2V -6 Lead-Free fpBGA 672 IND 92

LFE3-95E-7FN672I11.2V -7 Lead-Free fpBGA 672 IND 92

LFE3-95E-8FN672I11.2V -8 Lead-Free fpBGA 672 IND 92

LFE3-95E-6FN1156I11.2V -6 Lead-Free fpBGA 1156 IND 92

LFE3-95E-7FN1156I11.2V -7 Lead-Free fpBGA 1156 IND 92

LFE3-95E-8FN1156I11.2V -8 Lead-Free fpBGA 1156 IND 92

1.This device has associated errata. View www.latticesemi.com/documents/ds1021.zip for a description of the errata.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

Package Pins Temp. LUTs (K) Lead-Free prGA 672 ND 149 Lead-Free prGA 672 ND 149 Lead-Free prGA 672 ND 149 -6 Lead-Fvee prGA 1156 ND 149 -7 Lead-Free prGA 1156 ND 149 -8 Lead-Free prGA 1156 IND 1 -150EA-spFNpkgCTW and LFE3-150EA-spFNpkgiTW devices, (where sp is in same as ihe LFE3-150EA-spFNpkgC and LFEB-150EA-spFNp/(gl devices vespeciive ce Circuii) inSide the SERDES hard PCS in ihe TW device is not iunciionai b lamented in soft iP. XFiES pin on ihe TW device passes CDM lesimg ai 250V.

5-7

Ordering Information

Lattice Semiconductor LatticeECP3 Family Data Sheet

Part Number Voltage Grade Package Pins Temp. LUTs (K)

LFE3-150EA-6FN672I 1.2V -6 Lead-Free fpBGA 672 IND 149

LFE3-150EA-7FN672I 1.2V -7 Lead-Free fpBGA 672 IND 149

LFE3-150EA-8FN672I 1.2V -8 Lead-Free fpBGA 672 IND 149

LFE3-150EA-6FN1156I 1.2V -6 Lead-Free fpBGA 1156 IND 149

LFE3-150EA-7FN1156I 1.2V -7 Lead-Free fpBGA 1156 IND 149

LFE3-150EA-8FN1156I 1.2V -8 Lead-Free fpBGA 1156 IND 149

Part Number Voltage Grade Package Pins Temp. LUTs (K)

LFE3-150EA-6FN672ITW* 1.2V -6 Lead-Free fpBGA 672 IND 149

LFE3-150EA-7FN672ITW* 1.2V -7 Lead-Free fpBGA 672 IND 149

LFE3-150EA-8FN672ITW* 1.2V -8 Lead-Free fpBGA 672 IND 149

LFE3-150EA-6FN1156ITW* 1.2V -6 Lead-Free fpBGA 1156 IND 149

LFE3-150EA-7FN1156ITW* 1.2V -7 Lead-Free fpBGA 1156 IND 149

LFE3-150EA-8FN1156ITW* 1.2V -8 Lead-Free fpBGA 1156 IND 149

*Note: Specifications for the LFE3-150EA-spFNpkgCTW and LFE3-150EA-spFNpkgITW devices, (where sp is the speed and

pkg is the package), are the same as the LFE3-150EA-spFNpkgC and LFE3-150EA-spFNpkgI devices respectively, except as

specified below.

• The CTC (Clock Tolerance Circuit) inside the SERDES hard PCS in the TW device is not functional but it can be

bypassed and implemented in soft IP.

• The SERDES XRES pin on the TW device passes CDM testing at 250V.

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

Lattice“ emiconguctor Corporation A variety of technical noies for me LaniceECPS family are available on me Lattice websiie a1 www.larlicesemi.com. LatilceECPa sysCONFIG Usage Guide LatilceECPa SERDES/PCS Usage Guide LatilceECPa syle Usage Guide LatilceECPa svsCLOCK PLL/DLL Design and Usaqe Guide LatilceECPS Memory Usage Guide LatilceECPa HighrSgeed l/O lnierlace Power Consummion and Manaqemeni for LaiticeECPS Devices LatilceECPS sysDSP Usage Guide LatilceECPa Soft Error Deieciion SED) Usage Guide LatilceECPS Hardware Checklisi ndards refer to the following websites: CMOS, SSTL, HSTL): www.'edec.org :www.gci5ig.com

February 2009 Preliminary Data Sheet DS1021

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

www.latticesemi.com 6-1 DS1021 Further Info_01.0

For Further Information

A variety of technical notes for the LatticeECP3 family are available on the Lattice website at www.latticesemi.com.

• TN1169, LatticeECP3 sysCONFIG Usage Guide

• TN1176, LatticeECP3 SERDES/PCS Usage Guide

• TN1177, LatticeECP3 sysIO Usage Guide

• TN1178, LatticeECP3 sysCLOCK PLL/DLL Design and Usage Guide

• TN1179, LatticeECP3 Memory Usage Guide

• TN1180, LatticeECP3 High-Speed I/O Interface

• TN1181, Power Consumption and Management for LatticeECP3 Devices

• TN1182, LatticeECP3 sysDSP Usage Guide

• TN1184, LatticeECP3 Soft Error Detection (SED) Usage Guide

• TN1189, LatticeECP3 Hardware Checklist

For further information on interface standards refer to the following websites:

• JEDEC Standards (LVTTL, LVCMOS, SSTL, HSTL): www.jedec.org

•PCI: www.pcisig.com

LatticeECP3 Family Data Sheet

Supplemental Information

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

Lattice“ Semiconductor . Corporation Summary rallel burst mode Flash 250 Mbps to 230 Mbps ll't Embedded SERDES bul- d a footnote to indicate 230 Mbps applies to applications. r ECP3-17 in LatticeECPS Family Selection Guide table embedded memory lrom 552 to 700 Kbits in LatticeECPS lection Guide table pdated description for CLKFB in General Purpose PLL Diagram. orrected Primary Clock Sources text SSCIlOH. Corrected Secondary Clock/Control Sources text section. Corrected Secondary Clock Regions table. Corrected note below Detailed sysDSP Slice Diagram. Corrected Clock. Clock Enable. and Reset Resources text sectr Corrected ECP3-17 EBR number in Embedded SRAM mt LatticeECF'B Family table. Added On-Chip Termination Options for Input Modes Updated Available SERDES Quads per LatticeECF'B Updated Simplified Channel Block Diagram to diagram. Updated Device Configuration text sec Corrected software delault value of MC DC and Switching Characteristics Updated VCCDB Min/Max data r table. Corrected footnote 2 in sys table. Added added tooth teristics table. Added 2-to-1 Ge Updated E Latti intor

March 2010 Preliminary Data Sheet DS1021

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

www.latticesemi.com 7-1 DS1021 Revision History

Date Version Section Change Summary

February 2009 01.0 — Initial release.

May 2009 01.1 All Removed references to Parallel burst mode Flash.

Introduction Features - Changed 250 Mbps to 230 Mbps in Embedded SERDES bul-

leted section and added a footnote to indicate 230 Mbps applies to

8b10b and 10b12b applications.

Updated data for ECP3-17 in LatticeECP3 Family Selection Guide table.

Changed embedded memory from 552 to 700 Kbits in LatticeECP3

Family Selection Guide table.

Architecture Updated description for CLKFB in General Purpose PLL Diagram.

Corrected Primary Clock Sources text section.

Corrected Secondary Clock/Control Sources text section.

Corrected Secondary Clock Regions table.

Corrected note below Detailed sysDSP Slice Diagram.

Corrected Clock, Clock Enable, and Reset Resources text section.

Corrected ECP3-17 EBR number in Embedded SRAM in the

LatticeECP3 Family table.

Added On-Chip Termination Options for Input Modes table.

Updated Available SERDES Quads per LatticeECP3 Devices table.

Updated Simplified Channel Block Diagram for SERDES/PCS Block

diagram.

Updated Device Configuration text section.

Corrected software default value of MCLK to be 2.5 MHz.

DC and Switching

Characteristics

Updated VCCOB Min/Max data in Recommended Operating Conditions

table.

Corrected footnote 2 in sysIO Recommended Operating Conditions

table.

Added added footnote 7 for tSKEW_PRIB to External Switching Charac-

teristics table.

Added 2-to-1 Gearing text section and table.

Updated External Reference Clock Specification (refclkp/refclkn) table.

LatticeECP3 sysCONFIG Port Timing Specifications - updated tDINIT

information.

Added sysCONFIG Port Timing waveform.

Serial Input Data Specifications table, delete Typ data for VRX-DIFF-S.

Added footnote 4 to sysCLOCK PLL Timing table for tPFD.

Added SERDES/PCS Block Latency Breakdown table.

External Reference Clock Specifications table, added footnote 4, add

symbol name vREF-IN-DIFF.

Added SERDES External Reference Clock Waveforms.

Updated Serial Output Timing and Levels table.

Pin-to-pin performance table, changed "typically 3% slower" to "typically

slower".

LatticeECP3 Family Data Sheet

Revision History

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

nal Switching Characteristics. Family Timing Adders, Maximum Ho High Speed Data Transmitter, Channel Out- ck Function Performance, Register-to- d Power Supply Requirements. Data Specifications table. table, Serial Rapid l/O Type 2 Electrical and Timing section nal Description tables. Pin Information Summary tables and added footnote 1. hanged references ol “multi-boot" to “dual-boot“ throughout the data eet Updated On-Cnrp Programmable Termination bullets. Updated On-Chip Termination Options for Input Modes table. Updated On-Chip Termination figure. Switching risitcs Changed min/max data for FREFiPPM and added footnote 4 in SERDES External Reference Clock Specilication table. Updated SERDES minimum lrequency. nout Information Corrected MCLK to be HO and CCLK to be i in Signa DC and Switching Characterisitcs Corrected truncated numbers for Vccra and Vcooe i Operating Conditions table Architecture Corrected link in sysMEM Memory Block sec Updated information for On-Chip Progr fied corresponding figure. Added footnote 2 to On-Cnrp Pro lnput Modes table. Corrected Per Quadrant Pr DC and Switching Characterisitos Modified -8 Timing data for Write. EBR Output Ft Added ESD Per LatticeECPB Ex tDlEGDDFtv ‘ Lattice EC P tcoo sysC November 2009 01.5

7-2

Revision History

Lattice Semiconductor LatticeECP3 Family Data Sheet

May 2009

(cont.)

01.1

(cont.)

DC and Switching

Characteristics

(cont.)

Updated timing information

Updated SERDES minimum frequency.

Added data to the following tables: External Switching Characteristics,

Internal Switching Characteristics, Family Timing Adders, Maximum I/O

Buffer Speed, DLL Timing, High Speed Data Transmitter, Channel Out-

put Jitter, Typical Building Block Function Performance, Register-to-

Updated Serial Input Data Specifications table.

Updated Transmit table, Serial Rapid I/O Type 2 Electrical and Timing

Characteristics section.

Pinout Information Updated Signal Description tables.

Updated Pin Information Summary tables and added footnote 1.

July 2009 01.2 Multiple Changed references of “multi-boot” to “dual-boot” throughout the data

sheet.

Architecture Updated On-Chip Programmable Termination bullets.

Updated On-Chip Termination Options for Input Modes table.

Updated On-Chip Termination figure.

DC and Switching

Characterisitcs

Changed min/max data for FREF_PPM and added footnote 4 in

SERDES External Reference Clock Specification table.

Updated SERDES minimum frequency.

Pinout Information Corrected MCLK to be I/O and CCLK to be I in Signal Descriptions table

August 2009 01.3 DC and Switching

Characterisitcs

Corrected truncated numbers for VCCIB and VCCOB in Recommended

Operating Conditions table.

September 2009 01.4 Architecture Corrected link in sysMEM Memory Block section.

Updated information for On-Chip Programmable Termination and modi-

fied corresponding figure.

Added footnote 2 to On-Chip Programmable Termination Options for

Input Modes table.

Corrected Per Quadrant Primary Clock Selection figure.

DC and Switching

Characterisitcs

Modified -8 Timing data for 1024x18 True-Dual Port RAM (Read-Before-

Write, EBR Output Registers)

Added ESD Performance table.

LatticeECP3 External Switching Characteristics table - updated data for

tDIBGDDR, tW_PRI, tW_EDGE and tSKEW_EDGE_DQS.

LatticeECP3 Internal Switching Characteristics table - updated data for

tCOO_PIO and added footnote #4.

sysCLOCK PLL Timing table - updated data for fOUT

External Reference Clock Specification (refclkp/refclkn) table - updated

data for VREF-IN-SE and VREF-IN-DIFF

LatticeECP3 sysCONFIG Port Timing Specifications table - updated

data for tMWC.

Added TRLVDS DC Specification table and diagram.

Updated Mini LVDS table.

November 2009 01.5 Introduction Updated Embedded SERDES features.

Added SONET/SDH to Embedded SERDES protocols.

Architecture Updated Figure 2-4, General Purpose PLL Diagram.

Updated SONET/SDH to SERDES and PCS protocols.

Date Version Section Change Summary

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

ments table and footnotes Speed table. ce table PLL Timing table. ble ed Data Transmitter tables. gh-Speed Data Receiver table. footnote tor Receiver Total Jitter Tolerance Speciticaticn table. Periodic Receiver Jitter Tolerance Specification table. pdated SERDES External Reference Clock Specification table. pdated PCI Express Electrical and Timing AC and DC Characteristics Deleted Reference Clock table for PCI Express Electrical and Timing AC and DC Characteristics Updated SMF'TE AC/DC Characteristics Transmit table Updated Mini LVDS table. Updated RSDS table. Added Supply Current (Standby) table for EA device Updated Internal Switching Characteristics table. Updated Register-to-Register Performance ta Added HDMl Electrical and Timing Character Updated Family Timing Adders table Updated sysCONFIG Port Timing Spec Updated Recommended Operat Updated Hot Socket Specif Updated Single-Ended DC Updated TRLVDS tab Updated Serial Da Updated HDMl T Ordering information Added LFE industrial t March 2010 01.6 Architecture Adde DC and Switching Adde Characteristics Pincut lntorma Ordering |

7-3

Revision History

Lattice Semiconductor LatticeECP3 Family Data Sheet

November 2009

(cont.)

01.5

(cont.)

Architecture

(cont.)

Updated Table 2-13, SERDES Standard Support to include SONET/

SDH and updated footnote 2.

DC and Switching

Characterisitcs

Added footnote to ESD Performance table.

Updated SERDES Power Supply Requirements table and footnotes.

Updated Maximum I/O Buffer Speed table.

Updated Pin-to-Pin Peformance table.

Updated sysCLOCK PLL Timing table.

Updated DLL timing table.

Updated High-Speed Data Transmitter tables.

Updated High-Speed Data Receiver table.

Updated footnote for Receiver Total Jitter Tolerance Specification table.

Updated Periodic Receiver Jitter Tolerance Specification table.

Updated SERDES External Reference Clock Specification table.

Updated PCI Express Electrical and Timing AC and DC Characteristics.

Deleted Reference Clock table for PCI Express Electrical and Timing

AC and DC Characteristics.

Updated SMPTE AC/DC Characteristics Transmit table.

Updated Mini LVDS table.

Updated RSDS table.

Added Supply Current (Standby) table for EA devices.

Updated Internal Switching Characteristics table.

Updated Register-to-Register Performance table.

Added HDMI Electrical and Timing Characteristics data.

Updated Family Timing Adders table.

Updated sysCONFIG Port Timing Specifications table.

Updated Recommended Operating Conditions table.

Updated Hot Socket Specifications table.

Updated Single-Ended DC table.

Updated TRLVDS table and figure.

Updated Serial Data Input Specifications table.

Updated HDMI Transmit and Receive table.

Ordering Information Added LFE3-150EA “TW” devices and footnotes to the Commercial and

Industrial tables.

March 2010 01.6 Architecture Added Read-Before-Write information.

DC and Switching

Characteristics

Added footnote #6 to Maximum I/O Buffer Speed table.

Corrected minimum operating conditions for input and output differential

voltages in the Point-to-Point LVDS table.

Pinout Information Added pin information for the LatticeECP3-70EA and LatticeECP3-

95EA devices.

Ordering Information Added ordering part numbers for the LatticeECP3-70EA and

LatticeECP3-95EA devices.

Removed dual mark information.

Date Version Section Change Summary

SEE LatticeECP3-EA

DATA SHEET FOR

CURRENT INFORMATION

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