Working with SiC MOSFETS: Challenges and Design Recommendations

By Murray Slovick

Contributed By Digi-Key's North American Editors

For high-power applications such as grid conversion, electric vehicles, or home appliances, silicon carbide (SiC) MOSFETs have many advantages over their silicon IGBT counterparts, including faster switching speed, higher current density and lower on-state resistance. However, SiC MOSFETs come with their own list of concerns, including ruggedness, reliability, ringing in high-frequency applications, and fault handling.

For designers, the key to successfully applying SiC MOSFETs is to develop a strong understanding of the SiC MOSFETs unique operating characteristics and how it affects design. This article will provide that insight, along with implementation recommendations and solution examples.


To appreciate the capabilities of SiC MOSFETs it’s useful to compare them to their Si counterparts. SiC devices can block 10x more voltage than silicon, have a higher current density, can transition between the on and off states 10x faster, and have lower on-state resistance. For example, a 900 volt SiC MOSFET can provide the same on-state resistance as Si MOSFETs in a chip size 35x smaller (Figure 1).

Image of SiC MOSFETs offer lower on-state resistance and higher voltage capability

Figure 1: SiC MOSFETs (right) offer lower on-state resistance and higher voltage capability, compared to Si devices. (Image source: ROHM Semiconductor)

Standard silicon MOSFETs will exhibit well over two times the typical 25°C RDS(on) when operated at up to 150°C. When properly packaged, SiC MOSFETs can have a temperature rating of 200°C or more. The very high operating temperatures of SiC MOSFETs also simplifies thermal management, leading to reduced pc board form factors as well as improved system reliability.

Design challenges

SiC MOSFET technology can be a double-edged sword, however, bringing with it improvements as well as design challenges. Among the many challenges, engineers must be sure to:

  • Drive SiC MOSFETs optimally to minimize conduction and switching losses
  • Minimize gate losses. The gate driver needs to be capable of providing +20 volts and -2 volts to -5 volts negative bias, with minimum output impedance and high-current capability.
  • Pay attention to system parasitics, especially at the faster switching speed. This specifically refers to stray inductances and capacitances, beyond what is typically seen around Simodules.
  • Recognize that the output switching current rate (di/dt) is significantly higher with SiC MOSFETs than with Si MOSFETs. This can increase DC bus ringing, EMI, and output stage losses. High switching speeds can also result in voltage overshoots.
  • Meet reliability and fault-handling performance requirements for high-voltage applications

Let’s examine the main issues and how to account for them.

Conduction and switching loss

Among the main aspects influencing switching behavior are turn-off energy, turn-on energy, the so-called Miller effect, and gate drive current requirements.

Turn-off energy (Eoff) depends upon gate resistance (RG) and RGS(off) (voltage gate source, off). Eoff can be lowered by draining more current from the gate, by either reducing RG, or by using a negative bias gate voltage during off time. For this, the driver ICs for SiC MOSFETs should be able to manage a small negative gate voltage in order to provide a safe and stable off-state condition.

The turn-on energy is generally the process of charging the MOSFET parasitic capacitances to the voltage level required to achieve low RDS(on). Like turn-off energy, turn-on energy is also improved by reducing the RG. A graph of Eon vs Rg shows that when the gate resistance moves from 10 Ω to 1 Ω, the turn-on energy decreases almost by 40% (Figure 2).

Graph of Eon vs. R<sub>G</sub>; turn-on performance

Figure 2: Eon vs. Rg; turn-on performance is improved by reducing the gate resistance (Rg). (Image source: STMicroelectronics)

The Miller effect

If the voltage drop across the gate resistor exceeds the threshold voltage of the upper MOSFET in a half-bridge converter, a parasitic turn-on known as “Miller turn-on” or “Miller effect” occurs. In the presence of Miller turn-on, the reverse recovery energy (Err) can significantly impact the global switching loss.

To counter this, SiC MOSFET drivers can have a Miller clamp protection function included to control the Miller current during power stage switching in half-bridge configurations (Figure 3).

Schematic of STMicroelectronics Miller clamp protection connection

Figure 3: Miller clamping is a well-known technique to avoid parasitic dVds/dt triggered turn-on. The schematic shown is an example of a Miller clamp protection connection. (Image source: STMicroelectronics)

When the power switch is in the “Off” state, the driver operates to avoid the induced turn-on phenomenon that may occur due to gate capacitance when the other switch in the same leg is being turned on.

Reducing on-state resistance

A good low on-state resistance SiC MOSFET is ROHM’s SCT3030KLGC11, a third-generation device that operates at 1,200 volts and has an on-state resistance of 30 milliohm (mΩ). It uses a proprietary trench gate structure that reduces input capacitance by 35% and on-state resistance by 50%, compared with previous planar SiC MOSFETs.

The trench gate refers to a type of structure wherein a MOSFET gate is formed on the sidewall of a groove created on the chip surface. ROHM’s tests show that the third-generation solutions can shoot from 0 volts to 800 volts in about 50 nanoseconds (ns).

However, there is a parameter trade-off that designers need to be aware of: the newer devices are not as capable of withstanding short-circuit current. This is because the amount of silicon needed for a given on-state resistance has been cut approximately in half, versus previous generation devices. A smaller piece of silicon under short-circuit conditions doesn’t have as much mass to take the short for as long a period of time.

Gate drive requirements for SiC MOSFETs

SiC MOSFETs require a higher gate voltage swing than standard super-junction MOSFETs and IGBTs. Looking at STMicroelectronics’ SCT30N120, a 1200 volt, 80 mΩ (typical), SiC MOSFET, as an example, a higher (+20 volts) positive bias gate drive is recommended in order to minimize losses. It’s not advisable to drive the SiC MOSFET with more than +20 volts in the positive direction as the VGS absolute maximum rating is +25 volts. It is possible to go as low as +18 volts, but this increases the RDS(ON) by about 25% (@ 20 A, 25°C).

Depending on the application, a negative OFF gate voltage in the -2 volt to -6 volt range may also be required. The maximum supply voltage rating of the driver must be between 22 volts and 28 volts, depending on whether a negative OFF voltage is applied. Given that the gate charge required to switch the device is low, the higher voltage swing doesn’t affect the required gate drive power.

The gate current needed to turn a MOSFET on or off can be easily calculated using the gate charge, as listed on the relevant datasheet. For the SCT30N120, total gate charge (Qg) is typically 106 nanocoulombs (nC) at VDD = 800 V, ID = 20 A, VGS = -2 to 20 V. For maximum switching speed, the driver must be able to source or sink the gate peak current measured at RG = 1 Ω, VGS(on) = +20 V and VGS(off) = -2 V. In this case, the peak gate current is lower than 2 A in both (sink/source) cases.

Minimizing parasitics and EMI

The high-speed switching transients of a device provide additional energy to the parasitic inductance and capacitance that are present in a circuit. These parasitics form resonant circuits that can cause voltage and current overshoots and ringing. Voltage drops across even a few nanohenries of stray inductance can be a problem as voltage overshoots manifest at the time when one MOSFET is turned on, while the other is carrying free-wheeling current.

In silicon IGBTs, a current tail provides a certain amount of turn-off snubbing that reduces voltage overshoot and ringing. SiC MOSFETs have no tail, making the amount of drain voltage overshoot and parasitic ringing noticeably higher.

Designers can reduce the effects of these parasitics by:

  • Minimizing the conductor length
  • Placing the gate driver as close as possible to the MOSFET, and using stacked conductor geometries instead of side-by-side (co-planar) geometries

Another result of the high-speed switching is increased electromagnetic interference (EMI). This is due to the high rate of change (di/dt) values present when charging and discharging the gate capacitance of the MOSFETs, as well as the high-speed switching of the load current. Reducing ringing when switching SiC MOSFETs in high-frequency applications is important if EMI standards are to be met.

Reliability and fault handling

As oxide is used as the gate insulating layer in SiC power MOSFETs, it directly affects the reliability of the device. When increasing switching speeds, if the gate oxide is exposed to voltages exceeding the recommended operational values, it could lead to premature failure.

While problematic in the early days of SiC MOSFETs, there is considerable evidence that this issue is now well under control.

For example, Cree’s (Wolfspeed division) oxide layer is as reliable as those of Si MOSFETs1. Current gate oxide technology can achieve long-term reliability at high temperature operation, assuming the stress on the gate oxide is maintained within tolerable levels. According to Wolfspeed, the assessed lifetime for a gate to source voltage of 20 volts is ten million hours.

The short-circuit withstand time of SiC MOSFETs is typically around 3 microseconds (µs), so a fast detection and a fast shut down are therefore mandatory for reliable operation of SiC MOSFETs and long lifetime. In addition, repetitive short-circuit events can increase a SiC MOSFETs on-state resistance.

Getting started

Designers have a number of tools at their disposal to help them become familiar with SiC MOSFETs. One worth investigating is the Cree KIT8020CRD8FF1217P-1 SiC MOSFET Evaluation Kit (Figure 4). It is designed to demonstrate the performance of all Cree 1200 volt MOSFETs and Schottky diodes in standard TO-247 packages. It includes all the power stage parts needed to quickly assemble a Cree SiC MOSFET and diode-based power converter and get started with SiC devices in a half-bridge circuit.

Configurable to different power conversion topologies such as buck or boost, it provides easy access to critical test points for measurement including VGS, VDS and IDS.

General block diagram of Cree’s KIT8020CRD8FF1217P-1 SiC MOSFET eval kit

Figure 4: General block diagram of Cree’s KIT8020CRD8FF1217P-1 SiC MOSFET eval kit. The gate drive block with electrical isolation is designed on the board to drive SiC MOSFET Q1 and Q2. (Image source: Cree Semiconductor)

The kit includes a half-bridge configured evaluation board with two Cree 80 mΩ, 1200 volt MOSFETs and two 1200 volt, 20 Amp Schottky diodes, an extruded aluminum heatsink with mounting holes, isolated gate drivers, a ferrite bead, power supplies, and all the other components needed to quickly assemble the power stage.


Raising the operating frequency of a system by using fast switching SiC semiconductors will lead to such benefits as reduced losses over the economic lifetime of the product, reduced thermal management requirements, smaller inductor size and less filtering necessary to avoid EMI issues.

As shown, there are factors such as parasitics, on resistance, and fault handling that must be considered in order to take full advantage of SiC MOSFETs. However, awareness, the use of proven solutions and starter kits, and following good engineering practices will help avoid any issues and ensure a successful design.


  1. D. A. Gajewski, S. H. Ryu, M. Das, B. Hull, J. Young, J. W. Palmour, "Reliability Performance of 1200 V and 1700 V 4H-SiC DMOSFETs for Next Generation Power Conversion Applications", Materials Science Forum, Vols. 778-780, pp. 967-970.

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About this author

Murray Slovick

About this publisher

Digi-Key's North American Editors